Semiconductor integrated circuits

Details Semiconductor integrated circuits Semiconductor integrated circuits

1999-12-28

2003-01-28

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S374000, C257S396000, C257S401000, C257S623000, C257S900000, C438S135000

Reexamination Certificate

active

06512275

ABSTRACT:

The invention relates to semiconductor devices and more specifically to integrated semiconductor device circuits.
BACKGROUND OF THE INVENTION
In semiconductor integrated circuits, as the scale of integration increases, it is important to find new ways to reduce the area occupied by circuits while satisfying ever increasing demands for higher speed and lower power consumption.
For the majority of semiconductor integrated circuits produced today, transistors are fabricated within wells formed in a bulk semiconductor substrate. This method of fabrication places the following limitations, among others, on the integrated circuits produced therefrom: the area of substrate occupied by the transistor is not less than minimum lithographic dimensions; the width to length (W/L) ratio of the transistor is not greater than the dimensions defined in the plane of the substrate; and contact studs and metallization at a separate level are necessary to make a connection between each transistor and any other transistor.
Accordingly, it is an object of the invention to provide an apparatus including an active device formed in a substantially continuous mesa region of semiconductor material formed on one or more sides of an isolation region, in which the apparatus includes a conductive path formed in the mesa region which extends in a linear direction of the mesa region.
Accordingly, it is an object of the present invention to provide semiconductor integrated circuits in which active devices such as transistors therein have a W/L ratio which is controllable independently from the dimensions that the active devices extend in the plane of the substrate.
It is another object of the invention to provide integrated circuits in which multiple active devices are self-linked, i.e. do not require separate level metallization for linking.
Still another object of the invention is to provide integrated circuits which occupy very little area of the substrate as gauged by minimum lithographic dimensions.
SUMMARY OF THE INVENTION
These and other objects of the invention are provided by the semiconductor apparatus and method for making the same of the present invention. Accordingly, in a first embodiment, the semiconductor apparatus includes a first active device formed in a substantially continuous mesa region of semiconductor material formed on one or more sidewalls of an isolation region, and a conductive path which extends from the active device in a linear direction of the mesa. In a preferred embodiment of the invention, a plurality of active devices are formed in the mesa region and are electrically connected thereby to form circuits such as a logic gate, or a precharge/equalization device.
Preferably, the conductive path comprises a metal, and more preferably a refractory metal. Most preferably the conductive path contains a compound of the metal with the semiconductor material present therein, e.g. to form a compound such as tungsten silicide.
In another aspect of the invention, active devices are formed in first portions of a substantially continuous mesa region of semiconductor material and second portions lying between the active devices are allowed to remain as conductive paths which interconnect the active devices.
In another aspect of the invention, a plurality of tightly pitched, discrete, active devices is fabricated by forming a substantially continuous mesa region of semiconductor material on one or more sides of an isolation region; photolithographically defining a break in the mesa region; and forming active devices in broken portions of the mesa region.
In another aspect of the invention, a CMOS inverter is fabricated by forming a substantially continuous mesa region of semiconductor material on one or more sides of an isolation region; forming an n channel field effect transistor (NFET) and a p channel field effect transistor (PFET) in the mesa region, the NFET and PFET having gates linked by a common gate conductor and at least one source/drain region of the NFET and PFET being conductively connected by a conductive path formed in the mesa region; and forming a contact to the gate conductor for a voltage signal input and a contact to the conductive path for an inverter output contact.


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