Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2002-07-24
2004-08-17
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C327S530000, C327S535000, C327S538000
Reexamination Certificate
active
06777707
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuits, particularly to a circuit configuration of a voltage down converter.
2. Description of the Background Art
Reflecting the demand for multifunction circuitry and lower power consumption, attention is now focused on a circuit that has ASIC (Application Specific IC) circuitry and DRAM (Dynamic Random Access Memory) circuitry embedded in one chip (referred to as an eDRAM (embedded Dynamic Random Access Memory) circuit hereinafter).
Also, there is a demand for miniaturization of transistors in order to increase the scale of integration and high performance of the transistor. Circuitry is configured with two types of transistors differing in the oxide film thickness, i.e., a transistor with a thin gate oxide film and a transistor with a normal gate oxide film (also called thin film transistor and thick film transistor hereinafter) according to the application. Specifically, the entire area of circuitry is reduced by configuring a circuit that is driven at a high operating voltage with a thick film transistor and a circuit driven that is driven at a low operating voltage with a thin film transistor.
FIG. 12
is a schematic diagram of an eDRAM circuit
10000
. Referring to
FIG. 12
, eDRAM circuit
10000
includes DRAM circuitry
10
and ASIC circuitry
11
.
In ASIC circuitry
11
in eDRAM circuit
10000
of
FIG. 12
, a thin film transistor having a thin gate oxide film that is driven at a low operating voltage (approximately 1V to 2V) is employed. In DRAM circuitry
10
, two types of transistors driven at a high operating voltage and a low operating voltage, i.e., a thin film transistor and a thick film transistor, are employed according to the application of the control circuit. Specifically, a high voltage of at least the level of a voltage of an H (logical high) level plus a threshold voltage (approximately 3.6V) is applied to the gate of the transistor that forms the memory cell in DRAM circuitry
10
by boosting the word line in a data reading and writing mode. Such a high voltage to the gate of a thin film transistor will cause damage. Therefore, a thick film transistor is used for transistors configuring memory cells. The same applies to other embedded control circuits. A mixture of thick film and thin film transistors are employed in accordance with the application, and an external power supply voltage VDDH of high voltage and an external power supply voltage VDDL of low voltage are employed corresponding to respective transistors.
In circuitry that is related to control of higher accuracy, there is provided a control circuit formed of a thin film transistor that operates upon receiving a predetermined internal voltage generated within the system instead of directly using external power supply voltages VDDH and VDDL in DRAM circuitry
10
. A voltage down converter (also called a VDC circuit) is generally employed to generate such an internal voltage. Since this VDC circuit receives a high voltage VDDH for operation, the VDC circuit must be formed of a thick film transistor.
FIG. 13
is a schematic diagram of a conventional VDC circuit
3000
that generates a predetermined internal voltage with respect to a control circuit formed of a thin film transistor.
VDC circuit
3000
receives a reference voltage VREF to generate an internal voltage VDD
1
of a level identical to that of reference voltage VREF. VDC circuit
3000
includes a differential amplifier
100
, and a P channel MOS transistor P
5
.
Differential amplifier
100
generates an output voltage CMP according to the voltage difference between reference voltage VREF and internal voltage VDD
1
. Transistor P
5
is connected between external power supply voltage VDDH and a node N
14
, receiving output voltage CMP of differential amplifier
100
at its gate.
FIG. 14
shows a circuit structure of differential amplifier
100
.
Differential amplifier
100
includes P channel MOS transistors
101
and
102
, and N channel MOS transistors
103
-
105
.
N channel MOS transistor
105
is connected between a node N
3
and ground voltage GND, and receives a bias voltage BIAS at its gate. P channel MOS transistor
102
is disposed between external power supply voltage VDDH and a node N
5
, and has its gate connected to node N
4
. N channel MOS transistor
104
is disposed between nodes N
5
and N
3
, and receives reference voltage VREF at its gates. P channel MOS transistor
101
is disposed between external power supply voltage VDDH and node N
4
, and has its gate connected to node N
4
. N channel MOS transistor
103
is disposed between node N
3
and node N
4
, and receives an internal voltage VDD
1
at its gate. Differential amplifier
100
is supplied with a constant current corresponding to the voltage level of signal BIAS as the operating current. This differential amplifier
100
is of the so-called current mirror configuration, and provides an output voltage CMP according to the voltage difference between internal voltage VDD
1
and reference voltage VREF.
FIG. 15
shows a circuit configuration of a reference voltage generation circuit
200
that generates reference voltage VREF.
Reference voltage generation circuit
200
includes a constant current source
224
connected to external power supply voltage VDDH, and supplying a constant current Ids, and N channel MOS transistors
212
and
213
.
Each of N channel MOS transistors
212
and
213
provided in series between an output node N
7
and ground voltage GND is diode-connected. These diode-connected transistors function as resistance elements.
Reference voltage generation circuit
200
generates reference voltage VREF at output node N
7
. Reference voltage VREF corresponds to a value of constant current Ids supplied by constant current source
224
multiplied by the combined resistance of the number of stages of the diode-connected transistors. For example, if the combined resistance of transistors
212
and
213
functioning as resistance elements is RS
1
, the value of reference voltage VREF is set to constant current Ids×combined resistance RS
1
.
FIG. 16
is a VREF characteristic diagram of a reference voltage generation circuit. Reference voltage VREF exhibits a substantially constant level even if power supply voltage VDDH rises, as shown in FIG.
16
. Since the value of reference voltage VREF can be set based on constant current Ids of constant current source
224
, reference voltage generation circuit
200
is not easily affected by a change in the external power supply voltage. An accurate reference voltage VREF can be supplied steadily.
An operation of VDC circuit
3000
in a normal mode will be described here.
When internal voltage VDD
1
having the current consumed by the memory cell becomes lower than the voltage level of reference voltage VREF, the level of output voltage CMP, i.e., the gate voltage of P channel MOS transistor P
5
, is reduced. Accordingly, P channel MOS transistor P
5
is rendered conductive, whereby the level of internal voltage VDD
1
rises. When internal voltage VDD
1
becomes higher than the level of reference voltage VREF, the level of output voltage CMP rises. In response, P channel MOS transistor P
5
is rendered non-conductive, whereby the current supply at node N
14
is suppressed. Accordingly, internal voltage VDD
1
drops to the level of reference voltage VREF.
Thus a predetermined internal voltage VDD
1
generated within the system based on an external power supply voltage is generated by a VDC circuit. An accurate internal voltage VDD
1
is supplied to a control circuit formed of a thin film transistor.
In order to remove initial failure in advance, accelerated operation aging is applied on the device for a predetermined period of time to screen out any defective products. Burn-in testing is generally employed as one method of screening. The burn-in testing is a method of directly evaluating the dielectric film based on the actual device. By applying stress of high temperature and high electric field, v
Akiyama Mihoko
Fujii Nobuyuki
Morishita Fukashi
Okamoto Mako
Taito Yasuhiko
McDermott & Will & Emery
Nelms David
Renesas Technology Corp.
Tran Long
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