Semiconductor integrated circuit with reduction of self...

Details Semiconductor integrated circuit with reduction of self... Semiconductor integrated circuit with reduction of self...

2002-06-03

2003-12-16

Le, Thong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S229000

Reexamination Certificate

active

06665225

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit with a self refresh current which is reduced by an improved refreshing characteristic in a self refresh mode in a volatile device such as a DRAM requiring a refreshing operation.
2. Description of the Prior Art
Generally, in a semiconductor memory module or the like in which a semiconductor chip including a DRAM is mounted, a chip select signal CS is generated for selectively operating the DRAM in accordance with an upper significant bit of an address signal supplied from a microprocessor (CPU), and a refresh command signal is generated for giving a refresh timing on the basis of control signals such as a chip enable signal CE, a read enable signal RE, a row address strobe signal RAS, and a column address signal CAS supplied from the microprocessor (CPU). These generated chip select and refresh command signals are supplied to each DRAM.
Each DRAM has a refresh control function of determining a refresh mode on the basis of the strobe signals, setting a word line to a selection level and performing a refresh operation. To realize such a self refresh function, a semiconductor integrated circuit including a DRAM as a nonvolatile device in a chip has an address generating circuit and a self timer for measuring a self refresh cycle.
A memory cell array in a DRAM chip is generally divided into a plurality of banks, and only a selected part of the banks is operated in a read/write operation. However, in a refreshing operation, usually, all of the banks are concurrently operated, and therefore a peak current becomes large. As a result, in a DRAM module as well, a large peak current flows in the refreshing operation. This causes a Vdd/GND noise (i.e., power source noise), which results in an erroneous operation.
In a DRAM and the like device, it is conventionally desired to reduce current consumption (Icc6 or the like) in the self refresh mode. As a method of reducing the current consumption (Icc6), generally, there is employed a method of increasing a cycle of a self timer. For example, in a process of refreshing a DRAM, there is employed a method of switching a clock to a low frequency clock in a standby mode to thereby make the refresh interval longer.
In this method, however, there is a limitation in extending the cycle of the self timer, so that this method is insufficient. Specifically, a range of extending the cycle of the self timer is limited by a retention time of cell data (i.e., refresh retention time), and therefore the cycle of the self timer cannot be sufficiently extended.
However, in future, the consumption current (Icc6) is increasing as the memory capacity increases and accordingly the process become finer. Therefore, in order to realize lower power consumption of a device as well, it is an important subject to reduce the current consumption (Icc6) in the self refresh mode.
FIG. 5
shows a block configuration of a conventional DWL driver circuit. The DWL driver circuit has a transistor MOS
1
and a pair of opposing transistors MOS
2
and MOS
3
. As a gate signal for performing an ON/OFF control on the transistors, a gate signal (ZMWL) is supplied to the gates of the transistors MOS
1
and MOS
2
, and a gate signal (ZSDA) is supplied to the gate of the transistor MOS
3
. As a potential of a word line WL, a potential selected by the DWL driver circuit is applied. In an active state, an H-level potential of a sub decode signal SDA is supplied to the word line WL. In a standby state (non-active state), an L-level potential (=0 volt) of a ground potential GND is supplied.
In recent years, in studies regarding the cell data retention time (refresh cycle), as one of main factors of deteriorating the retention time of cell data, a GIDL (Gate Induced Drain Leakage) phenomenon is considered.
FIG. 6A
shows a model for explaining occurrence of the GIDL, and
FIG. 6B
shows a bias condition at the time of the GIDL occurrence. Conventionally, in the self refresh mode, a device is operated in the same bias condition as that in the normal mode. In
FIG. 6A
, a bit line BL side corresponds to a source side, a word line WL side corresponds to a gate side, and a storage node SN/SC corresponds to a drain side.
The potential of the bit line BL is switched between H and L levels in accordance with whether the bit line BL is selected or not. The gate in the standby state is set to a ground (GND) potential (=0 volt) level of the DWL driver circuit, and the word line WL is set to the L level (0 volt). The example shown in
FIG. 6B
shows a failure mode in which an error of the level from H to L occurs in one bit cell.
When an electric field is generated between the gate side in the standby state and the drain side (on the side of storage node SN/SC) to which the H level of cell data (array Vdd level) is written, the electric field between the gate and drain becomes strong in the vicinity of a gate oxide film. Consequently, a distortion occurs between energy bands of the substrate and drain in the vicinity of a channel substrate surface, and electric potential levels Ev and Ec shown in
FIG. 6B
approach each other, and electrons (−) and positive holes (+) transit between the bands, and a current leak is caused. That is, it is considered that a tunnel leak between bands occurs. When such a current leak occurs, retention time of cell data deteriorates. Therefore, the range of extending the cycle of the self timer is limited.
SUMMARY OF THE INVENTION
The invention has been developed to solve the problem by paying attention to the fact that the current leak of the GIDL component can be controlled by, in consideration of an inter-band tunnel leak phenomenon which occurs between a gate and a drain, changing a potential of a word line WL to thereby change an electric field generating between the gate and the drain and control the distortion ratio of the bands.
The invention employs such a method of controlling the current leak of the GIDL component. By setting the potential of a word line WL in the standby state to a low voltage for self refresh which is higher than a normal ground (GND) potential (=0 volt) only by a very small value, the potential difference between the word line WL and the drain (SC) is reduced. Accordingly, an object of the invention is to provide a semiconductor integrated circuit with a reduced current leak of the GIDL component, an improved refresh cycle (retention time of cell data), and a reduced self refresh current.
To achieve the object, one aspect of the present invention provides a semiconductor integrated circuit having a DRAM mounted thereon, which includes: a DWL driver circuit for selectively driving a word line, supplying a sub decode signal of an H level as a potential of the word line in an active state, and supplying an L-level signal of a ground potential in a standby state for a normal operation; and bias means for switching and connecting in a self refresh mode the potential of the word line to a potential of a low voltage for self refresh which is slightly higher than the ground potential.
In another aspect of the present invention, the bias means includes a self refresh GND switching circuit interposed between the DWL driver circuit and the ground potential and further includes a low voltage generating circuit connected to the self refresh GND switching circuit, for generating a low voltage for self refresh which is higher than the ground potential only by a very small value. In the self refresh mode, the self refresh GND switching circuit disconnects the word line from the ground potential and biases the potential of the word line to the low voltage value for self refresh generated by the low voltage generating circuit in a standby state.
With the configuration according to the present invention, the potential difference between the word line and the drain can be decreased, and the current leak of the GIDL component can be reduced. That is, t

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit with reduction of self... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit with reduction of self..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit with reduction of self... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3118578