Semiconductor integrated circuit with mixed gate array and stand

Details Semiconductor integrated circuit with mixed gate array and stand Semiconductor integrated circuit with mixed gate array and stand

1997-12-23

2000-04-25

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326101, H03K 19177

Patent

active

06054872&

ABSTRACT:
The present invention relates to a semicustom ASIC, in which a plurality of standard cell rows are arranged. The standard cell and basic cells used in a gate array are mixedly mounted on the same chip. Respective cell rows are composed of a plurality of standard cells with an empty space. The basic cells used in the gate array are arranged as dummy cells. They are disposed in wiring channel regions between the plurality of standard cells or empty spaces between the standard cells in a same standard cell row. Only the latter may be used if the channelless type standard cells are employed. A changing request can be satisfied by forming metal wiring layers on the gate array basic cells when there is a necessity of changing circuit design or pattern. Since the circuit can be modified without change of gate polysilicon regions and source/drain regions underlying the metal wiring layers, design and manufacture can be effected in a short period of time.

REFERENCES:
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patent: 4750027 (1988-06-01), Asami
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patent: 4811073 (1989-03-01), Kitamura et al.
patent: 4949275 (1990-08-01), Nonaka
patent: 4967100 (1990-10-01), Okutsu et al.
patent: 4969029 (1990-11-01), Ando et al.
patent: 5051917 (1991-09-01), Gould et al.
patent: 5155390 (1992-10-01), Hickman et al.

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