Semiconductor integrated circuit with low-power bus...

Details Semiconductor integrated circuit with low-power bus... Semiconductor integrated circuit with low-power bus...

1998-08-28

2001-01-16

Etienne, Ario (Department: 2781)

Electrical computers and digital data processing systems: input/

Intrasystem connection

C710S120000, C710S120000, C710S120000

Reexamination Certificate

active

06175886

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an LSI (large scale integrated circuit) chip capable of operating on low power, and particularly, to a low-power bus structure for LSI chips and a system for composing such a low-power bus structure.
2. Description of the Prior Art
An LSI chip has a core containing functional blocks that transfer data among them through a bus.
FIG. 1
shows a bus structure according to a prior art to connect functional blocks to one another. A bus
1009
is shared by the functional blocks
1001
,
1003
,
1005
, and
1007
. The functional blocks connect their output signals to the bus
1009
through respective bus drivers
1011
,
1013
,
1015
, and
1017
and receive input signals from the bus
1009
through respective buffers
1019
,
1021
,
1023
, and
1025
. For example, the functional block
1001
connects its output signal to the bus
1009
through the bus driver
1011
and receives an input signal from the bus
1009
through the buffer
1019
.
Control signals CONT
100
, CONT
200
, CONT
300
, and CONT
400
control the bus drivers
1011
to
1017
, respectively. In response to these control signals, the bus drivers determine connection states between the bus
1009
and the corresponding functional blocks. For example, the control signal CONT
100
is activated to connect the output of the functional block
1001
to the bus
1009
and is inactivated to disconnect the same from the bus
1009
. The other bus drivers work similarly.
Since the bus
1009
is shared, only a function block is allowed to send data, and during this operation, the other functional blocks are prohibited from sending data to the bus
1009
. To achieve this, a bus arbitrator
1027
is arranged to control the control signals CONT
100
to CONT
400
so that only one of them is activated. For example, when the functional block
1001
transfers data to the functional block
1007
, only the control signal CONT
100
is activated and the other control signals are inactivated so that only the output of the functional block
1001
is transferred to the functional block
1007
through the bus driver
1011
, bus
1009
, and buffer
1025
as indicated with an arrow A.
This bus structure has a problem of large power consumption. When data is transferred between two of the functional blocks, the whole parasitic capacitance of the bus
1009
is charged and discharged. If the parasitic capacitance is large, it consumes large power. The power consumption of a CMOS LSI is mostly dynamic and is caused by the charging and discharging of parasitic capacitance. The parasitic capacitance of a bus increases as the bus becomes longer and as the number of bus drivers and buffers connected to the bus becomes larger. Recent improvements in the performance of LSIs are coming with increasing the bus width in LSIs, i.e., the power consumption thereof. Portable information equipment that works on batteries is rapidly spreading. It is essential for such equipment to elongate battery life. To extend battery life, it is strongly required to lower the power consumption of LSI chips installed in the portable information equipment.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a low-power bus structure capable of reducing power consumption.
In order to accomplish the object, the present invention provides a bus structure shown in FIG.
2
. Functional blocks
1
,
3
,
5
, and
7
are arranged on an LSI chip and are connected to a bus
9
, which transfers data among the functional blocks. The bus
9
is divided into subsections
9
a
,
9
b
, and
9
c
. A pair of the functional blocks, for example,
1
and
7
that frequently transfer data between them is connected to the same subsection, for example,
9
b
. The subsections are provided with bidirectional bus drivers
29
and
31
to selectively electrically connect and disconnect the subsections.
If the frequency of mutual data transfer is high between a give pair of the functional blocks, the present invention transfers data between such functional data blocks after electrically disconnecting the subsection to which these functional blocks are connected from the other subsections with the use of the bidirectional bus drivers. As a result, only part of the parasitic capacitance of the whole bus is charged and discharged at this time. Compared with the prior art that always charges and discharges the entire parasitic capacitance of the bus, the present invention is capable of reducing the parasitic capacitance that is charged and discharged actually, to decrease total power consumption.


REFERENCES:
patent: 4604743 (1986-08-01), Alexandru
patent: 4922409 (1990-05-01), Schoellkopf et al.
patent: 5375097 (1994-12-01), Reddy et al.
patent: 5917336 (1999-06-01), Smith et al.

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