Semiconductor integrated circuit with buffer circuit and manufac

Details Semiconductor integrated circuit with buffer circuit and manufac Semiconductor integrated circuit with buffer circuit and manufac

1995-09-01

1997-03-25

Westin, Edward P.

Electronic digital logic circuitry

Tri-state

With field-effect transistor

326 83, 326 87, H03K 190948, H03K 1900

Patent

active

056148429

ABSTRACT:
A semiconductor integrated circuit with a buffer circuit is disclosed. The source of the first P(N)MOS transistor is connected to a voltage supply (ground), its drain being connected to an output terminal. The source of the first N(P)MOS transistor is connected to the ground (voltage supply), its drain being connected to the output terminal. The gate of the second P(N)MOS transistor is connected to the gate of the first NMOS transistor, its source being connected to the voltage supply (ground) and its drain being connected to the output terminal. The gate of the second N(P)MOS transistor is connected to the gate of the first PMOS transistor, at least one of its source and drain being floated. A controller responses to an enable signal and an input signal to apply control signals to the gates of the first PMOS and NMOS transistors. By these control signals, any one of the first PMOS and NMOS transistors is turned on based on the input signal level when the enable signal is on. Whereas both the first PMOS and NMOS transistors are turned off irrespective of the input signal level when the enable signal is off. The semiconductor integrated circuit further includes an input buffer connected the output terminal via a resistor. The input buffer applies a signal appearing at the output terminal to internal circuitry of the semiconductor integrated circuit.

REFERENCES:
patent: 4680487 (1987-07-01), Kobayashi
patent: 4697107 (1987-09-01), Haines
patent: 5450356 (1995-09-01), Miller

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