Semiconductor integrated circuit with a reduced skew and...

Details Semiconductor integrated circuit with a reduced skew and... Semiconductor integrated circuit with a reduced skew and...

2001-01-19

2003-04-01

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06543042

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit with a reduced clock skew and a layout method in design of a semiconductor integrated circuit with a reduced clock skew.
In recent years, semiconductor integrated circuits have been on the improvements in high density integration, large scale integration and high speed performances. It is necessary that the high density integration of the semiconductor integrated circuits is realized, whist a clock skew which may cause a hold defective is reduced to improve the reliability of the semiconductor integrated circuit.
As the high density integration has been progressed with change of the design rules from 0.25 micrometers-rule through 0.18 micrometers-rule to 0.13 micrometers-rule, a difference between a maximum value and a minimum value of an interconnection delay becomes remarkable, whereby a phase difference of the clock signals, for example, a clock skew is increased. If the phase difference of the clock signals or the clock skew becomes larger than a holding value of a flip-flop circuit, then a holding defective appears on the flip-flop circuits
FIG. 1
is a circuit diagram illustrative of first and second flip-flop circuits provided in a semiconductor integrated circuit to explain a holding defective of the flip-flop circuits. If a clock signal delay “N” becomes lower than a sum of a delay value “L”, a first internal delay value of a first flip-flop circuit F/F
1
, a delay value “M”, and a second internal delay value of a second flip-flop circuit F/F
2
, then the holding defective appears.
The clock skew value as the difference in delay of the clock signals is presumable but only after the layout and placement have been completed. For this reason, it is possible that after an automatic layout has been completed, the clock skew value is increased to cause the holding defective on the flip-flop circuit, whereby a malfunction of the flip-flop circuit may appear.
The following has been proposed to have solved the above problem. On the basis of delay informations after the automatic layout has been completed, then change of the circuit configuration, re-study and re-execution of the automatic layout are repeated until the clock skew is reduced.
FIG. 2
is a flow chart illustrative of a first conventional circuit design method.
In a step S
81
, the process is started.
In a step S
82
, a circuit design is carried out to form a net-list.
In a step S
83
, layout and placement of cells are executed by use of the net-list to form real interconnection data.
In a step S
84
, a post-layout delay information and a clock skew value are prepared on the basis of the real interconnection data and a previously prepared delay library.
In a step S
85
, a circuit design operation is confirmed and further a timing and the clock skew value are also confirmed.
In a step S
86
, it is verified whether or not any delay adjustment is needed. If the delay adjustment is needed, then the process will back to the step S
82
for changing the circuit design or the step S
83
for changing the cell layout. Those automatic layout processes will be repeated until the delay adjustment is not needed. If the delay adjustment is not needed, then the process is ended in a step S
87
.
In Japanese laid-open patent publication No, 10-327047, a second conventional technique is disclosed. A data input terminal or a data output terminal of a flip-flop circuit is coupled with a logic cell having a flip-flop circuit and being free of any delay circuit. Subsequently, a logic simulation is executed on the basis of the layout information. A timing information as the result of the logic simulation is investigated with reference to a design specification of the semiconductor integrated circuit to verify a possibility of malfunction due to the timing variation. The logic cell is replaced by another logic cell which has a delay circuit, so that the logic cell with the delay circuit is connected to the data input or output terminal of the flip-flop circuit.
It is considered that the clock signal is supplied from the common clock input terminal to the plural flip-flop circuits. A clock tree system causes that the number of the buffer circuits between the individual flip-flop circuits and the common clock input terminal becomes the same, whereby the clock skew value is reduced.
In this case, however, it is necessary to compensate the delay amount. A second conventional technique has been proposed.
FIG. 3
is a flow chart illustrative of a second conventional circuit design method.
In a step S
91
, the process is started.
In a step S
92
, a circuit design is executed to form a net-list.
In a step S
93
, layout and placement of cells are executed by use of the net-list to form real interconnection data.
In a step S
94
, a post-layout delay information and a clock skew value are prepared on the basis of the real interconnection data and a previously prepared delay library.
In a step S
95
, on the basis of the post-layout delay information and the clock skew value, a delay value of all paths of the clock-tree is extracted.
In a step S
96
, on the basis of the delay value of all paths of the clock-tree, a difference between the delay value of all paths of the clock-tree and a maximum value is calculated.
In a step S
97
, a delay circuit, which compensates to the calculated difference between the delay value of all paths of the clock-tree and the maximum value, is selected from a delay circuit library and the delay circuit is inserted into a logic cell to form a delay circuit cell.
In a step S
98
, a layout of the delay circuit cell is executed to form real interconnection data.
In a step S
99
, on the basis of the real interconnection data and a previously prepared delay circuit library, a delay information and a clock skew value are re-prepared to complete the circuit design process in a step S
100
.
The above first and second conventional circuit layout methods prepare individual logic cell libraries for individual paths to verify the individual delays, whereby a design turnaround time is long.
In case of the above clock tree shown in
FIG. 3
, the individual delay circuits, which compensate the difference between the delay value of all circuits of the clock tree and the maximum value, is inserted into the logic cell connected to the data input or output terminal of the flip-flop circuit. There are a large number of inserting positions into which the delay circuits are inserted, in case, a layout correction is difficult. As another method, it is possible to increase the length of the interconnections so that the fast path is adjusted to a delay path. This method is, however, unavailable to the high density interconnection region.
In the above circumstances, it had been required to develop a novel layout method in design of a semiconductor integrated circuit free from the above problem.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel layout method in design of a semiconductor integrated circuit free from the above problems.
It is a further object of the present invention to provide a novel layout method in design of a semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit.
It is a still further object of the present invention to provide a novel method in design of a semiconductor integrated circuit to reduce a clock skew to a half of a maximum clock skew value for increasing a design efficiency and shortening a turnaround time.
It is yet a further object of the present invention to provide a novel semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit.
The present invention provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps

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