Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-04-29
2004-12-28
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S019000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06836876
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit wiring condition processing method for finding a wiring condition that is used when wiring a semiconductor integrated circuit.
Conventionally, when wiring a semiconductor integrated circuit, it is necessary to keep the wiring delay time (hereinafter called “delay”) equal to or less than a predetermined delay reference value. To strictly meet the delay reference value requirements, a method such as the one disclosed in JP-A-6-259492 is known. In this method, the emitter follower current or the current switch current for the devices on each wiring path is controlled after wiring to keep the path delay variation to a minimum and to speed up the semiconductor integrated circuit. In addition, the use of a wide wiring line with a small wiring load capacity is generally known as a method for reducing the wiring delay.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a wiring condition processing method which reduces the power consumption of a circuit.
It is another object of the present invention to provide a wiring condition processing method which increases wiring channels.
It is still another object of the present invention to provide a wiring condition processing method capable of reducing variations in wiring delay times.
In the method, such as the one disclosed in JP-A6-259492 in which the emitter-follower current or the current switch current of a device is increased, there is a problem in that the circuit power consumption is increased to reduce the delay.
Conventionally, wide wiring lines have been used, for example, in all clock wires requiring strict delay restriction requirements. However, as more wide wiring lines are used, the number of wiring channels decreases. The decrease in the number of wiring channels results in some adverse effects such as wiring failures, more parallel non-wide wiring lines, and an increase in the chip size.
(1) To achieve the above objects, when the delay value of a virtual wiring line length based on the layout information on the devices on semiconductor substrate exceeds the reference value, the present invention adds information on the wide wiring line usage ratio to the path information to create wiring condition information.
This method, which uses wide wiring lines, reduces the power consumption. At the same time, this method sets up the usage condition for wide wiring lines and uses wide wiring lines only when this condition is satisfied, thus preventing the indiscriminate use of wide wiring lines and increasing the number of wiring channels.
(2) To achieve the above objects, when the delay value of the virtual wiring length based on the layout information on the devices on the semiconductor substrate exceeds the reference value, the present invention adds information on the usage ratio of a wiring layer with a small wiring load capacity to the path information to create wiring condition information.
This method, which uses a wiring layer with a small wiring load capacity, reduces the power consumption. At the same time, this method sets up the usage condition, thus reducing the use of wide wiring lines and increasing the number of wiring channels.
(3) To achieve the above objects, when the delay value of the virtual wirinq length based on the layout information on the devices on the semiconductor substrate exceeds the reference value, the present invention adds information on the usage ratio of parallel wiring lines to the path information to create wiring condition information.
This method, which restricts the use of parallel wiring lines, reduces the variation in delays and, at the same time, increases the number of wiring channels.
As described above, the method according to the present invention reduces the circuit consumption power and increases the number of wiring channels.
REFERENCES:
patent: 5896300 (1999-04-01), Raghavan
patent: 6604066 (2003-08-01), Hatsuda
patent: 6-259492 (1994-09-01), None
Hongyo Katsuaki
Mogaki Masato
Suzuki Katsuyoshi
Antonelli Terry Stout & Kraus LLP
Do Thuan
Hitachi , Ltd.
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