Semiconductor integrated circuit timing analysis apparatus...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C703S019000

Reexamination Certificate

active

10807286

ABSTRACT:
OCV coefficients in a path being an analysis target according to the number of gate stages are calculated in a coefficient arithmetically operating unit by canceling off a variation in delay in each gate in accordance with the number of gate stages in the target path, and timing analysis of the target path is performed in a timing analysis unit by using the OCV coefficient with the number of gate stages being considered, whereby a variation degree in the entire path is reduced in accordance with the number of gate stages in the target path, thus making it possible to carry out accurate timing analysis in consideration of the variation in a chip of a semiconductor integrated circuit.

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patent: 2004/0254776 (2004-12-01), Andou
patent: 2001-306647 (2001-02-01), None
patent: 03-005888 (2001-11-01), None
Hasegawa et al., “Timing Analysis System Heart for Large Scale Circuit (1) Procedure for Increasing Speed,” 35thNational Convention, Lecture Symposium (III), 1987, 5 pages.
Patent Abstracts of Japan of JP 63098042 A dated Apr. 28, 1988.
Patent Abstracts of Japan of JP 2002222232 A dated Aug. 9, 2002.

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