Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2005-08-30
2005-08-30
Auduong, Gene N. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700
Reexamination Certificate
active
06937533
ABSTRACT:
A semiconductor integrated circuit includes a regular cell array, a spare cell array, first and second memory circuits, a determining circuit, a generating circuit and a selecting circuit. When the regular cell array contains a defective regular memory cell, the defective regular memory cell is replaced with a spare memory cell in the spare cell array. Each of the first memory circuits stores data indicating whether an associated spare memory cell is used or not. Any of the second memory circuits stores address data indicating the address of the defective regular memory cell. The determining circuit determines whether each of the spare memory cells is used or not, based on the data stored in an associated first memory circuit. The generating circuit generates predetermined data. The selecting circuit selects and outputs the data generated by the generating circuit or address data stored in each of the second memory circuits.
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patent: 6400622 (2002-06-01), Fujiwara
patent: 6545921 (2003-04-01), Ohtani et al.
patent: 2000-182394 (2000-06-01), None
Ouellette, et al, “Shared Fuse Macro for Multiple Embedded Memory Devices with Redundancy,” IBM, Microelectronics Division, ASIC Development, Essex Junction, VT 05452, US, 4 pages, 2001 IEEE.
Hojo Takehiko
Sato Akikuni
Auduong Gene N.
DLA Piper Rudnick Gray Cary US LLP
Kabushiki Kaisha Toshiba
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