Semiconductor integrated circuit patterns

Details Semiconductor integrated circuit patterns Semiconductor integrated circuit patterns

2001-03-23

2004-04-27

Young, Christopher G. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Radiation modifying product or process of making

Radiation mask

C430S030000, C430S311000

Reexamination Certificate

active

06727026

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims benefits of priority under 35 USC § 119 to Japanese Patent Applications No. 2000-085244, filed on Mar. 24, 2000 and No. 2001-081140, filed on Mar. 21, 2001, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of designing semiconductor integrated circuit patterns; a photomask as used when a semiconductor integrated circuit is manufactured; and a method of manufacturing the semiconductor integrated circuit.
2. Description of the Related Art
With a high integration or high accelerating of a semiconductor device, the scale-down of a pattern is accelerated. In particular, with respect to a pattern for a contact/through hole (which is hereinafter shortened to read “a contact hole”) as formed in an interlayer dielectric, the diameter of a contact hole has a tendency to be scaled down, while the length between a contact hole and an adjacent one thereto also has a tendency to be shortened.
If the length between contact holes is shortened, it is commonly possible to densely arrange a pattern of contact hole. However, when the length between contact holes is uniformly shortened, an exposure margin is decreased; that is, in a photolithography process, a mask pattern is decreased in definition by light diffraction.
Therefore, recently, as a manner for improving a mask pattern in definition, a phase shift mask has been largely used. In particular, a half-tone type of phase shift mask attracts attention, wherein no auxiliary pattern is required, and a method of producing the mask is relatively simple. This half-tone type of phase shift mask is a photomask which comprises an opening and a translucent light shielding area, wherein a phase difference of 180° between a transmitted light at the shielding area and a transmitted light at the opening is provided.
Hereupon, as the shape of an opening pattern for a contact hole which is formed on a photomask, a square is usually utilized. A contact hole may be independently formed; however, a plurality of contact holes is often arranged in the form of a line. Even if a half-tone type of phase shift mask is used, when opening patterns for such contact holes that are arranged in the form of a line are transferred on a wafer, as explained hereinafter, a problem of a deformation of the transferred patterns due to a side lobe will be caused.
FIG. 9A
is a drawing illustrating an intensity distribution of an exposure light which passes through a photomask (
101
) which is a half-tone type of phase shift mask having a single square opening (
110
). At the center of the opening (
110
), a main lobe of the exposure light is formed, and a side lobe is formed also outside the opening. Incidentally, from the viewpoint of a plane, the main lobe and the side lobe are formed on a concentric circle. Therefore, when the light intensity of the side lobe is strong, a pattern of the side lobe may be transferred on a resist. Then, it becomes difficult to form a desirable designed pattern on a wafer.
The light intensity of the side lobe depends upon conditions for exposure, a type of a resist, a mask bias or the like. Therefore, by finding an optimum condition of each of them, the problem that a side lobe pattern is transferred on a resist on a wafer is commonly avoided, and thus a desirable pattern can be transferred on the wafer.
However, as shown in
FIG. 9B
, when a plurality of square openings (
110
A to
110
C) are closely arranged in the form of a line on a photomask (
101
), a side lobe as formed around each opening overlaps others, and thus the peak intensity of the side lobes is increased. In this case, it becomes very difficult to avoid a side lobe pattern as transferred on a wafer.
Accordingly, conventionally, when a plurality of contact holes is formed, it was necessary to make each space between patterns of contact holes on a wafer long to a certain length or more. Therefore, due to the limitation of the position of contact holes, the scale down of patterns has been impeded.
On the other hand, when rectangular opening patterns are formed on a photomask, the side lobe intensity is smaller as compared with the one when square opening patterns are formed. However, when a plurality of patterns are closely arranged, the problem that transferred patterns are deformed by an Optical Proximity Effect cannot be ignored, which is not limited to square or rectangular patterns.
For example, as shown in
FIG. 10A
, when a photomask (
103
) on which a plurality of fine rectangular patterns (
112
a
to
112
f
) are formed is used so as to carry out a photolithography process, patterns (
113
a
to
113
f
) as deformed by an Optical Proximity Effect are transferred on a resist (
105
) on a wafer, as shown in FIG.
10
B. In particular, when a space between rectangular patterns which are adjacent to each other is narrow, and the position of the upper end or the lower end of each side of the rectangular patterns is not trued up (for example,
112
b
to
112
f
), a deformation of transferred patterns by an Optical Proximity Effect is remarkable and complicated (for example,
113
b
to
113
f
).
Conventionally, for such a deformation caused by an Optical Proximity Effect, this deformation is previously taken into consideration, and an OPC (Optical Proximity Correction) processing by which a correction is added to a pattern on a mask has been carried out. However, an OPC processing for a plurality of patterns in which the position of the upper end or the lower end is not trued up, as shown in
FIG. 10A
, is complicated, and it is actually impossible to completely carry out a correction.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of designing patterns of a semiconductor integrated circuit, which is suitable for reducing a deformation of transferred patterns due to an exposure process and for forming patterns in accordance with a design.
It is another object of the present invention to provide a photomask that is suitable for precisely transferring designed patterns on a wafer.
It is a further object of the present invention to provide a semiconductor device as designed by using the above method of designing patterns of a semiconductor integrated circuit.
A first aspect of the present invention provides a method of designing patterns of a semiconductor integrated circuit which is characterized in that shape of each of a plurality of opening patterns corresponding to a plurality of contact holes is formed into a rectangular shape; and the contact holes are arranged in such a manner that a long side of each of the rectangular opening patterns is opposite to a long side of an adjacent rectangular opening pattern, and the position of ends of the long sides is trued up.
According to the first aspect of the present invention, rectangular opening patterns are formed on a mask that is used for forming patterns provided by the method. When the rectangular opening patterns are used, the intensity of a side lobe of an exposure light is weak, and thus a deformation of transferred patterns due to the side lobe can be reduced. Furthermore, a plurality of rectangular patterns are arranged in such a manner that both ends of a long side of each of them are trued up, and thus a precise Optical Proximity Effect correction can be relatively easily applied to a photomask pattern. Therefore, provided that an Optical Proximity Effect correction can be carried out, a design space between patterns can be made narrower. Accordingly, designed patterns can be precisely transferred on a wafer, and a circuit area can be reduced.
A second aspect of the present invention provides a method of designing patterns of a semiconductor integrated circuit which is characterized in that when a plurality of contact holes having rectangular or square opening patterns are present together, a space (DS) between adjacent patterns is decided on the basis of the shape of patterns, and the arrangement conditions of an

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit patterns does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit patterns, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit patterns will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3247673