Semiconductor integrated circuit manufacturing process...

Details Semiconductor integrated circuit manufacturing process... Semiconductor integrated circuit manufacturing process...

2009-03-20

2011-12-20

Whitmore, Stacy (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Testing or evaluating

C438S016000, C700S121000

Reexamination Certificate

active

08082536

ABSTRACT:
A method for evaluating a process of manufacturing a semiconductor integrated circuit including a deposition step and a polishing step after the deposition step, the method includes: dividing the semiconductor integrated circuit into a plurality of areas; determining a deposition height after the deposition step for each of the areas; and determining a risk value for each of the areas on the basis of a difference in the deposition height between each of the areas and its adjacent areas.

REFERENCES:
patent: 6905967 (2005-06-01), Tian et al.
patent: 7785983 (2010-08-01), Zia et al.
patent: 2004/0043560 (2004-03-01), Popp
patent: 2003-224098 (2003-08-01), None

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