Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-03-14
2004-08-17
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S013000
Reexamination Certificate
active
06779157
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-074782 filed on Mar. 15, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor integrated circuit and a technique of extracting parameters of a circuit element model used for a circuit simulation in designing a semiconductor integrated circuit.
2. Description of the Related Art
Semiconductor integrated circuits, in particular, LSIs such as high-frequency analog circuits, analog-digital circuits, and high-speed digital circuits involve fine patterns made by, for example, photolithography on semiconductor substrates. Testing these circuits requires a lot of time and money if they must actually be produced for the testing. To minimize testing time and cost, simulations are carried out to confirm the physical and electrical behaviors of the circuits and the circuit elements employed in the circuits before manufacturing. Simulations involved in the designing and development of a semiconductor integrated circuit include a process simulation to simulate the manufacturing processes, impurity/defect profiles, and geometries of circuit elements (or the devices); a device simulation to simulate the device behaviors of the circuit elements; and a circuit simulation to simulate the circuit performance.
The process simulation is carried out based on the conditions of each process and finds the impurity distributions and structures of semiconductor elements formed by the process. Based on the data provided by the process simulation, the device simulation is carried out to find the device behaviors of the semiconductor devices. Based on the data provided by the process and device simulations, the circuit simulation is carried out to find the circuit performance, or the electric characteristics of the semiconductor integrated circuit.
The circuit simulation employs a circuit element model representing the electric characteristics of a semiconductor element of a target integrated circuit, and based on the circuit element model, calculates potential levels and current values to occur at nodes of the integrated circuit. The circuit element model consists of numerical expressions representing the operation principles of the element and parameter values determined from manufacturing conditions. An operation to determine parameter values of a circuit element model according to electric characteristics measured on actual semiconductor elements is called “parameter extraction.” Correctly carrying out parameter extraction is important to provide an accurate circuit element model and secure the reliability of a circuit simulation.
For example, parameter extraction of a circuit element model of, for example, a MOSFET frequently employs an optimization technique. The optimization technique employs a nonlinear optimization algorithm such as a Newton-Raphson method to determine parameter values of the circuit element model. The optimization technique is easily applied to any circuit element model. However, it has a disadvantage of involving local solutions of poor accuracy when handling many parameters. To overcome this disadvantage, a local optimization technique is employed to extract parameters of a circuit element model such as a BSIM3 model involving many parameters.
Parameter extraction according to a related art employing the local optimization technique will be explained with reference to FIG.
1
.
Step S
201
measures the electric characteristics of actual semiconductor elements according to various bias conditions and element dimensions. Step S
202
classifies the measured electric characteristics according to the bias conditions and element dimensions. Step S
203
selects sensitive parameters related to the classified electric characteristics. Step S
204
carries out local optimization operations to narrow down and determine values of the selected parameters according to the classified electric characteristics. Step S
205
checks to see if the determined parameter values can sufficiently reproduce the actually measured electric characteristics. If the determination in step S
205
is affirmative, step S
207
provides the determined parameter values as the parameter values of the circuit element model. If the determination in step S
205
is negative, step S
206
carries out a global optimization operation to determine parameter values. Instead of step S
206
, step S
204
may again be carried out to determine parameter values.
Parameter extraction employing the local optimization technique will be explained in more detail with reference to a BSIM3 model.
The BSIM3 model expresses a MOSFET and includes parameters that are effective only when the channel length L of the MOSFET is short and the parameters are independent of the channel length L. For example, a partial expression P to calculate a threshold voltage of the MOSFET is as follows:
P=P
0
+P
1
/L
(1)
where P
0
and P
1
are parameters. If the channel length L of the MOSFET is sufficiently larger than the parameter P
1
, the influence of P
1
is small and P is nearly equal to P
0
. In this case, electric characteristics actually measured on MOSFETs having sufficiently long channel lengths are effective in narrowing down the parameter P
0
. Thereafter, the parameter P
1
is narrowed down from electric characteristics actually measured on MOSFETs having short channel lengths.
In this way, the parameter extraction employing the local optimization technique considers only a small number of sensitive parameters in each step, thus overcoming the disadvantage of the nonlinear optimization algorithm.
It is ideal for the local optimization technique that the sensitivity of any parameter that is not extracted in a given step and is to be extracted later is reduced to zero, realizing a perfectly localized state in the given step. In practice, however, it is difficult to realize a perfectly localized state. In the above example, a value of the parameter P
0
extracted first will greatly deviate from a true value depending on the value of the parameter P
1
extracted later, even if the channel length L is greatly extended.
As a result, each parameter extraction step of the local optimization technique involves calculation noise caused by parameters that are not determined in the step. Such calculation noise accumulates, enlarging the error step by step, and gradually deteriorating the accuracy of the parameter values determined. In the above example, absorbing error in the parameter P
0
using a parameter P
1
with short channel lengths increases errors with respect to large channel lengths.
Parameter extraction employing the local optimization technique, therefore, frequently requires global optimization and repetitive calculations.
Global optimization and repetitive calculations usually involve solution divergence and poor local solutions, and therefore, are incapable of correctly extracting parameters of a circuit element model or securing unique parameter values.
FIG. 2
is a graph showing a drain voltage vs drain current characteristic of a MOSFET involving such inaccurate solutions. This graph shows that electric characteristics provided by a circuit simulation based on inaccurate local solutions greatly deviate from actually measured electric characteristics.
Extraction accuracy of the parameters of a circuit element model seriously influences the semiconductor development stage of determining manufacturing conditions and designing a circuit. To reduce the cost and time of product development and improve the efficiency thereof, it is necessary to provide a technique of correctly extracting parameters of a circuit element model.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, an apparatus for extracting parameters of a circuit element model that represents a semiconductor element used for a circ
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