Semiconductor integrated circuit manufacturing method and...

Details Semiconductor integrated circuit manufacturing method and... Semiconductor integrated circuit manufacturing method and...

2008-06-03

2008-06-03

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07383527

ABSTRACT:
A semiconductor integrated circuit manufacturing method and semiconductor integrated circuit manufacturing apparatus are provided that implement automatic placement that reflects constraints provided regarding parasitic elements and inter-element variation provided in a real-valued range. A netlist is prepared in advance, a permissible range setting process sets a permissible range relating to elements, a floor plan process creates a floor plan that satisfies the set permissible range using the netlist, an automatic placement process places elements using the created floor plan and extracts routing constraints that realize a permissible range for parasitic elements, and a routing process performs routing in accordance with the extracted routing constraints.

REFERENCES:
patent: 6099581 (2000-08-01), Sakai
patent: 6701506 (2004-03-01), Srinivasan et al.
patent: 6772404 (2004-08-01), Tanaka
patent: 7093208 (2006-08-01), Williams et al.
patent: 7137097 (2006-11-01), Aji et al.
patent: 2004/0243964 (2004-12-01), McElvain et al.
patent: 10-092938 (1998-04-01), None
patent: 2002-093912 (2002-03-01), None
patent: 2003-085224 (2003-03-01), None
patent: 2004-178285 (2004-06-01), None
patent: 00/50767 (1999-07-01), None
patent: 99/50767 (1999-07-01), None
English Language Abstract of JP 2003-085224.
English Language Abstract of JP 2002-093912.
English Language Abstract of JP 2004-178285.
English Language Abstract of JP 10-092938.
U.S. Appl. No. 11/202,863 to Shimura, filed Aug. 19, 2005.

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