Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-07-22
2001-03-13
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06202195
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of laying out a semiconductor integrated circuit (SIC) with the aid of a computer. It more particularly pertains to an SIC layout technique for placing and interconnecting digital logic circuits or like components of a semiconductor integrated circuit.
In the design of large-scale integrated circuits (LSIs), it is required to meet limitations on the propagation delay time taken for a signal to propagate from one circuit to another and it is also very important to provide a semiconductor integrated circuit of minimum layout area, for the aspects of performance and costs. As the circuit scale of SIC increases the operating frequency thereof likewise increases. This results in an increase in the severity of a delay limitation imposed on the propagation delay time in a design phase. In an initial layout of a semiconductor integrated circuit, it is very important to modify the initial layout by reducing the signal propagation delay time of a wire involving a violation of the delay limitation, in order to cancel the delay limitation violation.
A conventional technique is discusses. When a layout is completed, the capacitance and resistance values of laid-out wires are exactly grasped and, based on the values, the signal propagation delay time of each wire is calculated. When a violation of the delay limitation is found, i.e., when any wire is found to have a signal propagation delay time in excess of a predetermined delay time, there are two ways of achieving a reduction of the signal propagation delay time. In the first way, a transistor in charge of driving a wire involving a violation of the delay limitation is replaced by another transistor having greater driving performance. In the second way, a violational wire is rerouted in order to reduce the length thereof.
The world of SIC enters now the deep-submicron age. As the cross-sectional area of wires is reduced, the resistance thereof increases. Additionally, the reduction of wire width and the reduction of wire spacing result in an increase in interwire capacitance (the capacitance between two adjacent wires), which therefore increases the total wire capacitance. Such increases in the total wire capacitance and in the wire resistance result in a longer signal propagation delay time. In regard to the signal propagation delay, wire delay becomes dominant in comparison with circuit component delay.
Accordingly, the foregoing conventional technique of making a change in the transistor driving performance may not be a very effective way of canceling violations of the delay limitation when wire delay becomes dominant.
For the case of rerouting a wire involving a violation of the delay limitation, it is also necessary to reroute its neighboring wires even when they are conformable to the delay limitation. Further, such rerouting may produce new violations of the delay limitation. Accordingly, the number of times such rerouting is carried out is increased. This is very time consuming. Much time is required to complete a design, and there is the possibility that repetition of the processing of rerouting will not make every wire free from a violation of the delay limitation.
SUMMARY OF THE INVENTION
Bearing in mind the above-described problems with the prior art techniques, the present invention was made. Accordingly, it is an object of the present invention to provide an improved layout method for a semiconductor integrated circuit in cases where the delay of wires is dominant in comparison with the delay of elements in regard to the signal propagation delay. More specifically, in accordance with the present layout method, the resistance and capacitance of wire is reduced in order of effectively canceling violations of the wire delay limitations, and the number of process steps required for re-design can be reduced without having to perform a process of rerouting a wire to reduce the length thereof.
With a view to achieving the above-noted object, in the layout method of the present invention a layout is generated based on a predetermined design limitation imposed on the wiring such as wire spacing defined between wires and wire width. If there is found a violational wire involving a violation of the design limitation, then the severity of the design limitation is relaxed so as to cancel the violation.
The present invention provides a method for the layout of a semiconductor integrated circuit, said layout method comprising:
(a) a layout step of laying out, in conformance with a predetermined design limitation, wires for interconnecting components which together form a circuit;
(b) a delay judging step of checking, on the basis of information representing a layout result obtained in said layout step, each of said laid-out wires for the presence of a violation of a predetermined delay limitation for the limitation of a signal propagation delay time; and
(c) a design limitation modifying step of making a change in said predetermined design limitation on the basis of said layout result information and a result of said judging step.
It is preferred in the layout method that the delay judging step includes a delay limitation violating wire extracting step of extracting, from among the laid-out wires, a violational wire in violation of the predetermined delay limitation, and the design limitation modifying step includes a delay limitation violation canceling step of making a change in the design limitation imposed on the violational wire in order to cancel the delay limitation violation.
It is preferred in the layout method that:
a wire spacing defined between two adjacent wires is predetermined to serve as the design limitation; and
the delay limitation violation canceling step includes a wire spacing modifying step of subjecting a wire located next to the extracted wire in violation of the delay limitation to parallel displacement in order to extend a wire spacing defined between the violational wire and the neighboring wire to above the predetermined wire spacing.
It is preferred in the layout method that:
a wire width is predetermined to serve as the design limitation; and
the delay limitation violation canceling step includes a wire width modifying step of extending, based on the layout result information and the information about the violational wire, the width of the violational wire and parallelly displacing the remaining other wires a distance equal to the widened width.
It is preferred in the layout method that:
the layout step lays out the wires on the basis of a predetermined design limitation with such allowance for most of the laid-out wires to meet the predetermined delay limitation;
the delay judging step includes an affording wire extracting step of extracting, from among the laid-out wires, an affording wire having a signal propagation delay time which meets the predetermined delay limitation; and
the design limitation modifying step including:
a design limitation changing step of increasing the severity of the predetermined design limitation imposed on the extracted affording wire; and
a compaction step of modifying, based on the revised design limitation, a layout around the affording wire in order to achieve a reduction in layout area.
It is preferred in the layout method that:
a wire spacing defined between two adjacent wires is predetermined to serve as the design limitation; and
the compaction step includes a wire spacing modifying step of subjecting a wire located next to the extracted affording wire to parallel displacement in order to reduce a wire spacing defined between the affording wire and the neighboring wire to below the predetermined wire spacing.
It is preferred in the layout method that:
a wire width is predetermined to serve as the design limitation; and
the compaction step includes a wire width modifying step of reducing the width of the affording wire and parallelly displacing the remaining other wires a distance equal to the reduced width.
The present invention provides a semiconductor integrated circuit comprising a plurality of co
Fukui Masahiro
Shinomiya Noriko
Tanaka Masakazu
Kik Phallaka
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Smith Matthew
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