Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement
Reexamination Certificate
2001-07-11
2003-06-10
Nelms, David (Department: 2815)
Static information storage and retrieval
Read/write circuit
Including specified plural element logic arrangement
C365S226000
Reexamination Certificate
active
06577543
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit. More particularly, the present invention relates to a semiconductor integrated circuit including a plurality of macros that can be operated although their operational voltages are different from each other.
2. Description of the Related Art
In order to make a data transmission speed between a DRAM (Dynamic Random Access Memory) and a logic circuit faster, a logic in memory is used in which the DRAM and the logic circuit are integrated on the same semiconductor chip.
There may be a case that a burn-in is performed on this logic in memory, in order to improve the reliability, similarly to other semiconductor integrated circuits. When the burn-in is performed on the logic in memory, a power supply voltage higher than a sent power supply voltage in a normal operation is sent to the logic in memory, and the operation is carried out in atmosphere at a high temperature. Thus, the deterioration at a defective portion is accelerated to thereby bring about a potential defect in a short time.
When the burn-in is performed on the logic in memory, the DRAM and the logic circuit need to receive the power supply voltages different from each other. This is because the DRAM and the logic circuit have the structures of the semiconductor elements included in them and the manufacturing processes that are different from each other. For example, the thicknesses of gate oxide films of MOS (Metal Oxide Semiconductor) transistors included in the DRAM and the logic circuit are typically different from each other. Thus, it is necessary to perform the burn-in while sending the different power supply voltages to the DRAM and the logic circuit, in order to obtain the fault lives at the same level between the DRAM and the logic circuit. At this time, a power supply voltage higher than that of the logic circuit is typically sent to the DRAM.
At this time, if the DRAM to which the high power supply voltage is sent outputs a signal to the logic circuit to which the low power supply voltage is sent, there may be the fear of a break of a semiconductor element included in the logic circuit. For example, let us consider the DRAM mixture semiconductor integrated circuit, in which a DRAM having a gate oxide film having a film thickness of 9 nm and a logic circuit having a gate oxide film having a film thickness of 6 nm are mixed. It is necessary to send a power supply voltage of 4.5 V to the DRAM at the operation of the burn-in. On the other hand, a power supply voltage of 3.5 V is sent to the logic circuit at the operation of the burn-in. The DRAM to which the power supply voltage of 4.5 V is sent outputs a signal having an amplitude of 4.5 V to the logic circuit. However, the maximum rated voltage of the logic circuit having the gate oxide film having the film thickness of 6 nm is 4.0 V. Thus, there may be the fear the break of this logic circuit when the signal having the amplitude of 4.5 V outputted by the DRAM is inputted.
It is necessary to protect the logic circuit from being damaged, when the DRAM to which the high power supply voltage is sent outputs the signal having the same amplitude as the high power supply voltage, to the logic circuit to which the low power supply voltage is sent, at the operation of the burn-in.
The above-mentioned situation similarly occurs in a semiconductor integrated circuit in which two macros to which different power supply voltages are sent are placed on a single chip. When the semiconductor integrated circuit containing the two macros having the different operational voltages is operated, it is desirable to protect the break of the semiconductor element included in the macro having the lower operational voltage, by sending a signal having a high voltage from the macro having the higher operational voltage to the macro having the lower operational voltage.
By the way, the related technique is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 10-247397).
FIG. 1
shows the configuration of the known semiconductor integrated circuit disclosed thereby. A known semiconductor integrated circuit
101
is provided with a memory mat
102
, a low decoder
103
, a low driver
104
, a column decoder
105
, a column driver
106
, a sense amplifier
107
, a low address buffer
108
, a column address buffer
109
, a data input buffer
110
, a data output buffer
111
, an input output control circuit
112
, an oscillator
113
, a booster power supply circuit
114
, a level sensor
115
and a control circuit
116
.
The known semiconductor integrated circuit
101
stops sending a booster power supply voltage V
pp
from the booster power supply circuit
114
when a burn-in test is carried out, and thereby protects the normal circuit elements included in the low decoder
103
and the like from being damaged. If the burn-in test is not done, the booster power supply voltage V
pp
is sent from the booster power supply circuit
114
to the low decoder
103
. On the other hand, if the burn-in test is done, a power supply voltage is sent to the low decoder
103
from an external portion of the semiconductor integrated circuit
101
, and the booster power supply voltage V
pp
is not sent from the booster power supply circuit
114
. Thus, it is possible to protect the break of the normal circuit elements, when an excessively high voltage is sent to the low decoder
103
.
In the logic in memory in which the logic circuit and the DRAM that can be operated although their operational voltages are different from each other are mixed, there may be further a case of an occurrence of an erroneous operation, depending on a timing when the power supply voltages are sent to the DRAM and the logic circuit, respectively, when the power supply is turned on.
This is because the operation of the DRAM is unstable until the power supply voltage sent to the DRAM reaches a certain degree of a voltage, after the power supply is turned on. Thus, this unstable operation may cause a data inputted to the logic circuit from the DRAM to be a data in which an input to the logic circuit is not assumed. The input of such a data to the logic circuit may result in the occurrence of the erroneous operation in the logic circuit.
Moreover, although the power supply voltage sent to the logic circuit does not reach a certain degree of a voltage, if the DRAM starts its operation and outputs a signal to the logic circuit, an improper voltage may be applied to the semiconductor element included in the logic circuit, and a latch-up state may be induced.
It is desirable to protect such an erroneous operation from being brought about when the power supply is turned on.
SUMMARY OF THE INVENTION
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to protect the break of the semiconductor element included in the macro having the lower operational voltage, by outputting a signal from the macro having the higher operational voltage to the macro having the lower operational voltage, when the semiconductor integrated circuit containing the two macros having the different operational voltages is operated.
Another object of the present invention is to protect the break of the semiconductor element included in the macro having the lower operational voltage, by outputting a signal to the macro on which the burn-in is performed while the lower power supply voltage is sent, from the macro on which the burn-in is performed while the higher power supply voltage is sent, in the semiconductor integrated circuit including the two macros on which the burn-in is performed while the different power supply voltages are sent.
Still another object of the present invention is to protect the break of the semiconductor element included in the logic macro, by outputting a signal to the logic macro on which the burn-in is performed while the lower power supply voltage is sent, from the DRAM macro on which the burn-in is performed while the higher power supply vo
Katten Muchin Zavis & Rosenman
NEC Corporation
Nelms David
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