Semiconductor integrated circuit including a DRAM and an...

Details Semiconductor integrated circuit including a DRAM and an... Semiconductor integrated circuit including a DRAM and an...

1999-09-17

2003-06-24

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S306000, C257S309000

Reexamination Certificate

active

06583458

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a capacitor and a fabrication process thereof.
A DRAM is a high-speed semiconductor memory device that stores information in a capacitor formed therein monolithically in the form of electric charges. Thus, DRAMs are used extensively in information processing apparatuses such as a computer as a memory device.
In these days, there is a demand for a semiconductor device in which a DRAM and an analog circuit device are formed monolithically on a common semiconductor substrate. Such an analog circuit device generally includes a capacitor formed in the monolithic state.
FIG. 1
shows the construction of a conventional DRAM
10
.
Referring to
FIG. 1
, the DRAM
10
is formed on a Si substrate
11
on which a memory cell region
10
A and a peripheral region
10
B are formed, wherein each of the memory cell region
10
A and the peripheral region
10
B includes an active region defined by a field oxide film
12
. Further, in the active region defined in the cell region
10
A by the field oxide film
12
, there are formed polysilicon gate electrodes
13
A-
13
C on respective gate oxide films
13
a
-
13
c
as word lines WL. In the substrate
11
, there are formed diffusion regions
11
a
-
11
e
adjacent to the gate electrodes
13
A-
13
C as represented in
FIG. 1
, wherein each of the gate electrodes
13
A-
13
C carries a pair of side wall insulation films. This side wall insulation film may be omitted.
Similarly, there is formed a gate electrode
13
D in the peripheral region
10
B via a gate insulation film
13
d
, and diffusion regions
11
f
and
11
g
are formed in the substrate
11
adjacent to the gate electrode
13
D. Further, there is formed a high-concentration diffusion region
11
h
in the peripheral region
10
B in correspondence to a region isolated by the field oxide film
12
, and there is formed a capacitor electrode
13
E on the foregoing high-concentration diffusion region
11
h
via an intervening insulation film
13
e
. It should be noted that the insulation film
13
e
corresponds to the gate insulation film
13
d
, of the gate electrode
13
D. As a result, the insulation film
13
e
form, together with the capacitor electrode
13
E and the diffusion region
11
h
, a capacitor C of the analog circuit device that is formed in the peripheral region
10
B.
It should be noted that the gate electrodes
13
A-
13
D, the word line WL, and further the capacitor electrode
13
E are covered by a first interlayer insulation film
14
formed on the substrate
11
so as to continuously cover the foregoing regions
10
A and
10
B, and contact holes
14
A-
14
C are formed in the interlayer insulation film
14
so as to expose the diffusion regions
11
b
,
11
d
and
11
f
respectively. It should be noted that the contact holes
14
A-
14
C have respective side walls covered by side wall insulation films
14
a
-
14
c
, and bit line electrodes
15
A and
15
B are provided on the interlayer insulation film
14
so as to cover the contact holes
14
A and
14
B. Further, an electrode
15
C is formed on the interlayer insulation film
14
so as to cover the contact hole
14
C. Thereby, the side wall insulation film
14
a
prevents the short-circuit between the electrode
15
A and the electrode
13
A in the case the position of the contact hole
14
A is offset. The side wall insulation films
14
b
and
14
c
function similarly.
Further, the electrodes
15
A-
15
C are covered by a second interlayer insulation film
16
formed on the interlayer insulation film
14
, and contact holes
16
A and
16
B are formed in the interlayer insulation film
16
so as to expose the diffusion regions
11
a
and
11
c
in the memory cell region
10
A. The contact holes
16
A and
16
B are formed with respective side wall insulation films
16
a
and
16
b
, and polysilicon accumulation electrodes
17
A and
17
B are formed on the interlayer insulation film
16
so as to cover the contact holes
16
A and
16
B respectively. Thereby, the side wall insulation films
16
a
and
16
b
prevent the short-circuit between the accumulation electrode
17
A or
17
B with the adjacent gate electrode
13
A or
13
B.
In the memory cell region
10
A, it should be noted that the accumulation electrodes
17
A and
17
B are covered by a dielectric film
18
, and the dielectric film
18
in turn is covered by a polysilicon opposing electrode
19
. Further, the polysilicon opposing electrode
19
is covered with a third interlayer insulation film
20
that covers also the foregoing peripheral region
10
B continuously, and a contact hole
20
A and a contact hole
20
B are formed in the interlayer insulation film
20
such that the contact hole
20
A exposes the electrode
15
C and such that the contact hole
20
B exposes the electrode
13
E. Further, electrodes
21
A and
21
B are formed on the interlayer insulation film
20
respectively in correspondence to the contact holes
20
A and
20
B. Further, interconnection patterns
21
C and
21
D are formed on the interlayer insulation film
20
. Thereby, the accumulation electrodes
17
A and
17
B form, together with the dielectric film
18
thereon and the opposing electrode
19
, respective memory cell capacitors.
The DRAM
10
of
FIG. 1
, however, has suffered from a drawback in that there tends to appear a large step height between the memory cell region
10
A and the peripheral region
10
B as a result of the repeated etching processes for forming the memory cell capacitors in the memory cell region
10
A. Further, such a stepped part at the boundary of the memory cell region
10
A and the peripheral region
10
B tends to invite accumulation of irregular polysilicon residue, which may cause various unpreferable effects such as short-circuit.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a semiconductor device including a memory cell region, in which a memory cell capacitor is formed, and a peripheral region where no such a memory cell capacitor is formed, wherein the step between the memory cell region and the peripheral region is minimized.
Another object of the present invention is to provide a semiconductor device including a memory cell region, in which a memory cell capacitor is formed, and a peripheral region where no such a memory cell capacitor is formed, wherein the problem of irregular polysilicon pattern remaining at a stepped part formed between the memory cell region and the peripheral region is effectively eliminated.
Another object of the present invention is to provide a fabrication process of a semiconductor device that includes a memory cell region, in which a memory cell capacitor is formed, and a peripheral region where no such a memory cell capacitor is formed, wherein a capacitor is formed in the peripheral region without increasing the number of the mask steps.
Another object of the present invention is to provide a semiconductor device, comprising:
a substrate defined thereon a first region and a second region;
an interlayer insulation film formed on said substrate so as to cover said first and second regions; and
a capacitor formed on said interlayer insulation film in said first region; and
wherein said interlayer insulation film includes, in said first region, a stepped part defined by a groove having a bottom surface lower in level than a surface of said interlayer insulation film in said second region.
According to the present invention, the problem of etching of the second region, which tends to occur in the semiconductor device that has the first region, or memory cell region, including therein a capacitor and further the second region or a peripheral region, when patterning the capacitor in the first region, is successfully avoided by protecting the second

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