Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-04-08
2002-01-08
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S017000, C326S119000
Reexamination Certificate
active
06337580
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit in which transistors for cutting-off a subthreshold current are added to feed lines and/or grounding lines which supply electrical potential to a logic gate circuit group in driving circuits of a semiconductor memory device.
2. Description of the Related Art
In the conventional semiconductor integrated circuit, in accordance with forming a minute semiconductor element, a subthreshold current flowing when the element is turned off is a problem. The subthreshold current is a current which flows even when the element is turned off. If the subthreshold current is left as it is, an erroneous operation of the circuit or the like is caused.
For example, in a word driver of a semiconductor memory devices, a gate circuit having a large driving power is used to drive a word line, and an influence of the subthreshold current is large so that a problem such that a consumption of a current is increased is caused.
In order to solve the problem caused by the subthreshold current, as disclosed in IEEEJ. Solid-State Circuit, vol. 28, No. 11, p.1105, November 1993, for instance, it is proposed that a transistor for cutting-off the subthreshold current is serially inserted to a feed line for applying a voltage to the semiconductor device element.
The conventional semiconductor integrated circuit to which the transistor for cutting-off the subthreshold current is added will now be described with reference to FIG.
5
.
A semiconductor integrated circuit as shown in
FIG. 5
is a selecting circuit of a word line in a dynamic random access memory (DRAM) and is constructed by: a word driver
600
; a decoder
500
; and n transistors
511
,
512
, . . . , and
51
n for cutting-off the subthreshold current (in the following, abbreviated to cut-off transistors). The word driver
600
is divided into n blocks
531
,
532
, . . . , and
53
n. Each of the blocks is constructed of m driving circuits
5411
to
541
m,
5421
to
542
m, . . . , and
54
n
1
to
54
nm each constructed of arbitrary logic circuits. Each of the outputs of the driving circuits
5411
to
541
m,
5421
to
542
m, . . . , and
54
n
1
to
54
nm is connected to each word line of the DRAM. By activating one driving circuit in accordance with input address signals, one word line is selected. Each of the cut-off transistors
511
,
512
, . . . , and
51
n is serially connected between a power source Vcc and each of feed lines L
50
, L
51
, . . . , and L
5
n of the blocks
531
,
532
, . . . , and
53
n of the word driver. The decoder
500
decodes a part of input address signals, sets one of signals &PHgr;
1
, &PHgr;
2
, . . . , and &PHgr;n to the low level, and sets one of the cut-off transistors
511
,
512
, . . . , and
51
n into a driving state. Thus, a current is supplied to the feed line to which the driving circuit selected in accordance with the input address is connected.
According to the construction, when word driver
600
is inactivated, all of the cut-off transistors
511
,
512
, . . . , and
51
n are turned off, so that no current flows through the feed lines L
50
, L
51
, . . . , and L
5
n. When the word driver
600
is activated, no current is supplied to non-selected blocks
531
,
532
, . . . , and
53
n. Consequently, damage by the subthreshold current can be avoided.
However, in the conventional semiconductor integrated circuit as shown in
FIG. 5
, in a state where the cut-off transistors
511
to
51
n are turned off and the word driver
600
is disconnected from the power source Vcc, there is a case where the subthreshold current flows in the word driver
600
and electric potentials of the feed lines L
51
to L
5
n drop. In such a case, a problem such that the word driver
600
is activated slowly is caused. That is, for instance, in case when the inputted address signals are decoded and the driving circuit
5411
in the word driver
600
is selected, the level of an output &PHgr;
1
of the decoder
500
becomes low. The cut-off transistor
511
is then turned on and, first, the feed line L
50
is charged. After that, the driving circuit
5411
is operated. As mentioned above, a problem such that even if the decoding signal of the address signal is inputted to the word driver
600
, the driving circuit can not be operated promptly is caused.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a semiconductor integrated circuit which can suppress a subthreshold current upon inactivation of a logic gate circuit group in a word driver or the like and can activate the logic gate circuit group at high speed.
A semiconductor integrated circuit of the present invention comprises:
a first feed line;
a second feed line;
a first power source line for applying a first electric potential to the first feed line;
at least one logic circuit connected between the first feed line and the second feed line and outputting a signal of a predetermined logic level in accordance with a logic level of an input signal;
a first transistor having a first conductivity and having a current path between the first power source line and the first feed line; and
a second transistor having the first conductivity and connected in parallel to the first transistor.
The first transistor is in a conductive state when the logic circuit is in an operation state and is in a non-conductive state when the logic circuit is in a standby state.
The second transistor is changed from a non-conductive state to a conductive state before the first transistor is changed from a non-conductive state to a conductive state.
A driving power of the first transistor is larger than that of the second transistor.
Further, a semiconductor integrated circuit of the present invention comprises:
a semiconductor integrated circuit comprising:
a memory cell array having a plurality of word lines;
a first decoder decoding address signals in response to a /RAS signal to output first decoding signals;
a plurality of feed lines;
a word driver having a plurality of blocks, each of which has at least one driving circuit, each of the driving circuits being connected with an associated one of the plurality of feed lines, each input terminal of the driving circuits receiving an associated one of the first decode signals and each output terminal of the driving circuits being connected to an associated one of the word lines, and
a cut-off circuit having a second decoder which decodes a part of the address signals to output second decoding signals, a plurality of first transistors, each of which is serially connected to associated one of the plurality of feed lines, each control electrode of the plurality of first transistors receiving an associated one of the second decoding signals, a plurality of second transistors, each of which is connected in parallel to each of the plurality of first transistors associated with it.
Control electrodes of the plurality of second transistors receive the /RAS signal.
Driving powers of the plurality of first transistors are larger than those of the plurality of second transistors.
According to this construction, when an electric potential of a feed line drops upon standby of a logic circuit by a subthreshold leakage current of the logic circuit, the feed line is charged prior to activation of the logic circuit, so that the activation of the logic circuit can be executed at a high speed.
REFERENCES:
patent: 5583457 (1996-12-01), Horiguchi et al.
patent: 5726946 (1998-03-01), Yamagata et al.
patent: 5751651 (1998-05-01), Ooishi
patent: 5-210976 (1993-08-01), None
patent: 8-83487 (1996-03-01), None
Kitsukawa, et. al., “256-Mb DRAM Circuit Technologies for File Applications”, IEEE Journal of Solid-State Circuits, vol. 28, No. 11, Nov. 1993, pp. 1105-1111.
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