Semiconductor integrated circuit having three wiring layers

Details Semiconductor integrated circuit having three wiring layers Semiconductor integrated circuit having three wiring layers

1998-10-19

2000-12-05

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

257204, 257208, 257211, H01L 2710

Patent

active

061570524

ABSTRACT:
A high melting point metal wiring layer, a second aluminum wiring layer, and a third aluminum wiring layer are stacked on transistors forming an inverter train of a hierarchical power supply structure respectively. The high melting point metal wiring layer is employed as a local wire for connecting the transistors with each other, the second aluminum wiring layer is employed as a local bus wire and a hierarchical power supply wire, and the third aluminum wiring layer is employed as a main bus wire and a power supply wire to intersect with the respective wires. Consequently, the wiring layers are easy to lay out, while no main bus region is required dissimilarly to the prior art and it is possible to reduce the layout area.

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patent: 5686746 (1997-11-01), Iwasa
Arimoto et al., "A 34ns 16Mb DRAM with controllable voltage down convertor", ESSCIRC Proceeding, Sep. 1991, pp. 21-24.
Horiguchi et al., "Switched-Source Impedance CMOS Circuit for Low Standby Subthreshold Current GIGA-Scale LSI'S"1993 Symposium on VLSI Circuit, Dig. of Tech. Papers, pp. 47-48.

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