Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2002-03-01
2002-12-03
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S758000, C257S728000
Reexamination Certificate
active
06489671
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit for high-speed operation, and more particularly, to three-dimensional interconnection wiring structure forming the semiconductor integrated circuit.
2. Description of the Related Art
Monolithic Microwave Integrated Circuit (MMIC) for comprising high frequency devices such as a High Electron Mobility Transistor (HEMT) or a Hetero-junction Bipolar Transistor (HBT), unlike a conventional silicon integrated circuit, needs high frequency wave guides for its interconnection lines. A microstrip line has been conventionally used for high frequency interconnection lines because it has stable wiring characteristics and low dispersion characteristics which means that frequency dependence of propagation constant is weak.
FIG. 1
is a cross-sectional view of a high frequency wave-guide for a 3-dimensional MMIC of prior art, particularly using multilayer microstrip lines. As shown in
FIG. 1
, the multilayer MMIC of prior art has a grounded plate
3
on a surface insulating layer
2
formed on the surface of a semiconductor substrate, and the grounded plate
3
is coupled with each of interconnection layers
5
formed on the respective insulating layers
4
to form the respective microstrip lines. The multilayer MMIC of prior art has an advantage in high-density integration over a usual MMIC having interconnection lines laid out on a single plane. However, signal propagation time in the high frequency interconnection lines depends significantly upon not only effective length of interconnection layers but also geometrical relationship with each other, particularly between the interconnection layers and the grounded plate. Therefore, it is not easy to feed an identical signal from a single node to plural nodes with identical timing. Nevertheless, there has been no report on multilayer interconnection lines for high frequency signals in consideration for signal timing. Additionally, it is not allowed that any conductive layer is laid out between the grounded plate and a microstrip line coupled therewith, which considerably restricts freedom of circuit layout design for high-density integration.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an MMIC having a 3-dimmensional tournament tree shaped multilayer interconnection lines, whereby a single electric signal on the uppermost interconnection layer can be fed to plural electrodes on the lowest interconnection layer with identical timing.
It is a further object of this invention to provide a 3-dimmensional MMIC having a smaller chip area with the same design rule and higher speed operation than prior art, in which electric feeding lines are allowed to overlap other interconnection layers.
In accordance with the stated objects, one aspect of the present invention is a multilayer interconnection structure for a 3-dimmensional MMIC, in which a semiconductor device for high frequency operation comprises a semiconductor substrate having an insulating layer on the surface thereof, a grounded plate formed on the semiconductor substrate connecting to a ground potential, a plurality of laminated interconnection layers formed on the grounded plate, the plurality of laminated interconnection layers being insulated from each other and also the grounded plate by insulating layers therebetween, and a vertical interconnection layer for connecting each immediately opposed upper and lower pair of the plurality of laminated interconnection layers in a through-hole penetrating the corresponding one of the insulating layers therebetween, the vertical interconnection layer being disposed at an electric center point of each of the plurality of laminated interconnection layers on a first surface of the corresponding one of the plurality of laminated interconnection layers, and at each end of the corresponding one of the plurality of laminated interconnection layers on a second surface of the corresponding one of the plurality of laminated interconnection layers opposing to the first surface.
REFERENCES:
patent: 5300798 (1994-04-01), Yamazaki et al.
patent: 5789807 (1998-08-01), Correale, Jr.
patent: 5973554 (1999-10-01), Yamasaki et al.
patent: 6034433 (2000-03-01), Beatty
patent: 6100573 (2000-08-01), Lu et al.
patent: 6175161 (2001-01-01), Goetz et al.
Aoki Yoshio
Baba Osamu
Gotoh Muneharu
Mimino Yutaka
Armstrong Westerman & Hattori, LLP.
Clark Sheila V.
Fujitsu Quantum Devices Limited
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