Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-06-25
2003-03-25
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S226000
Reexamination Certificate
active
06538936
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly to a structure of a boosted power supply generating circuit.
2. Description of the Background Art
Conventionally, for a semiconductor integrated circuit such as a DRAM (Dynamic Random Access Memory), a boosted power supply has been widely used to eliminate the influence of a threshold voltage of a transistor. In the DRAM, a boosted power supply Vpp is primarily used as a word line voltage or the like.
FIG. 14
is a block diagram showing a boosted power supply generating circuit
500
(hereinafter referred to as a Vpp generating circuit).
Vpp generating circuit
500
includes a detector circuit
100
, a ring oscillator circuit
200
, and a pump circuit
300
.
Detector circuit
100
detects any decrease in its voltage below a prescribed level due to current consumption of the semiconductor integrated circuit or the like for generating a signal &PHgr;
1
in generating Vpp.
An exemplary ring oscillator circuit
200
is shown in FIG.
15
.
Ring oscillator circuit
200
includes an NAND circuit
201
, a delay circuit
206
having inverters
202
to
205
connected in series, and an inverter
207
.
Ring oscillator circuit
200
receives signal &PHgr;
1
for repeatedly generating pulse signal &PHgr;
2
.
An exemplary pump circuit
300
is shown in FIG.
16
.
Pump circuit
300
includes capacitors
301
,
302
, and
303
, an inverter
304
, and N channel transistors
305
,
306
,
307
, and
308
.
In pump circuit
300
, capacitor
301
is arranged between nodes N
1
and N
3
. N channel transistor
305
is arranged between an external power supply source Ext. Vcc (hereinafter referred to as Vcc) and node N
3
, having its gate connected to external power supply source Vcc. N channel transistor
306
is arranged between external power supply source Vcc and node N
4
, having its gate connected to node N
3
. N channel transistor
307
is arranged between external power supply source Vcc and node N
5
, having its gate connected to node N
3
. Inverter
304
is arranged between nodes N
1
and N
2
. Capacitor
302
is arranged between nodes N
2
and N
5
. Capacitor
303
is arranged between nodes N
2
and N
4
. N channel transistor
308
is arranged between nodes N
4
and N
6
, having its gate connected to node N
5
. Vpp is supplied to each portion of the circuit from node N
6
.
Pump circuit
300
receives output signal &PHgr;
2
from ring oscillator circuit
200
for generating Vpp by a pumping operation of capacitors
301
,
302
, and
303
.
The operation of Vpp generating circuit
500
shown in
FIG. 14
will be described with reference to a time chart of FIG.
17
.
Detector circuit
100
is set to output signal &PHgr;
1
at “L” if its voltage is at a desired level (at or higher than a detection level) in generating Vpp.
Detector circuit
100
detects any decrease in Vpp below a prescribed level due to power consumption of the semiconductor integrated circuit, and outputs signal &PHgr;
1
at “H.”
If the decrease in Vpp is detected, output signal &PHgr;
1
at “H” is input from detector circuit
100
, and therefore ring oscillator circuit
200
repeatedly outputs pulse signal &PHgr;
2
at “H” in response to input signal &PHgr;
1
at “H” until Vpp attains to a prescribed level by a pumping operation which will later be described (
FIG. 17
shows that one pumping operation restores Vpp).
If no decrease in Vpp is detected, output signal &PHgr;
1
at “L” is input from detector circuit
100
, and therefore ring oscillator circuit
200
outputs signal &PHgr;
2
at “L.”
At the time, in pump circuit
300
, node N
1
is at “L,” and node N
2
is at “H” because of inverter
304
.
Node N
3
is precharged to a level of power supply voltage Vcc−Vth (Vth is a threshold voltage of N channel transistor
305
), and capacitor
301
is charged.
Nodes N
4
and N
5
are at a level of Vcc−2Vth (Vth is a threshold voltage of N channel transistors
306
and
307
).
If detector circuit
100
detects any decrease in Vpp, it outputs signal &PHgr;
1
at “H.”
Ring oscillator circuit
200
operates in response to signal &PHgr;
1
at “H,” and outputs signal &PHgr;
2
at “H.”
At the time, node N
1
is at “H,” and the pumping operation of capacitor
301
brings node N
3
to a level of 2Vcc−Vth, so that N channel transistors
306
and
307
are fully turned on.
Node N
2
attains from “H” to “L” because of inverter
304
.
Thus, although the voltage levels at nodes N
4
and N
5
temporarily decrease, they are precharged to the Vcc level when N channel transistors
306
and
307
are turned on.
Thus, capacitors
302
and
303
are charged to the Vcc level.
Subsequently, when output signal &PHgr;
2
from ring oscillator circuit
200
attains to “L,” node N
2
attains to “H” because of inverter
304
.
The pumping operation of capacitors
302
and
303
causes nodes N
4
and N
5
to attain to the 2Vcc level.
Then, N channel transistor
308
is turned on and electric charges are supplied to node N
6
. As a result, the voltage level at node N
6
rises.
A stress test is performed on a semiconductor integrated circuit to assure reliability, in which a high electric field is applied to an oxide film. In the above described Vpp generating circuit, reliability of capacitors
301
,
302
, and
303
must also be assured. In a stress test mode, the semiconductor integrated circuit is maintained in a stand-by mode and detector circuit
100
is inactivated by a Test signal shown in FIG.
14
. At the time, output signals &PHgr;
1
and &PHgr;
2
, respectively from detector circuit
100
and ring oscillator circuit
200
, are both at “L.” Thus, in the stress test mode, nodes N
1
and N
2
of the pump circuit
300
are always at “L” and “H,” respectively. Accordingly, capacitors
302
and
303
are subject to weaker stress as compared with capacitor
301
.
Having the above described structure, Vpp generating circuit
500
of a conventional semiconductor integrated circuit suffers from a problem that a desired level of stress cannot be applied to each capacitor in the pump circuit in a stress test mode for assuring reliability.
SUMMARY OF THE INVENTION
The present invention provides a Vpp generating circuit which ensures that a capacitor is reliably tested.
A semiconductor integrated circuit of the present invention includes: a plurality of memory cells arranged in a matrix; a memory cell array region having a plurality of word lines arranged corresponding to rows; and a plurality of bit lines arranged corresponding to columns; a pump circuit generating by a plurality of capacitors a boosted voltage supplied to the memory cell array region; and a test circuit controlling a level of stress applied to the plurality of capacitors in the pump circuit.
Preferably, the test circuit is controlled by a test signal.
Particularly, the test signal controls levels of stress applied to the plurality of capacitors.
According to the above described semiconductor integrated circuit, a desired level of stress can be applied to each capacitor in the pump circuit in a stress test mode, so that the semiconductor integrated circuit is provided with enhanced reliability.
Particularly, the test circuit controls the levels of stress applied to the plurality of capacitors simultaneously by the test signal.
According to the semiconductor integrated circuit of the present invention, desired levels of stress can be simultaneously applied to capacitors of the pump circuit in the stress test, so that the efficiency of the stress test and the reliability of the semiconductor integrated circuit increases.
Particularly, the test signal is input from an external signal pin.
Particularly, the test signal is input from an external pad.
Preferably, there is further provided a test signal generating circuit for internally generating the test signal.
Particularly, the test signal generating circuit generates a test signal in response to input from the external signal pin.
Particularly, the test signal generating circuit generate
Hayakawa Goro
Tanaka Koji
Lebentritt Michael S.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Phung Anh
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