Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1995-06-02
1996-07-16
Westin, Edward P.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326101, H03K 19096
Patent
active
055370616
ABSTRACT:
A semiconductor integrated circuit has a parallel conductor transmission line including a plurality of signal paths branching at a node. The signal paths have phase compensation sections for creating a phase constant of the transfer constant thereof, where the phase constant is inversely proportional to the length of the signal paths. The phase compensation sections are implemented by covering a microstrip line by a layer having a high dielectric constant or implemented by a second ground conductor disposed opposite to the microstrip conductor with a thin layer of a high dielectric constant. The integrated circuit comprises a plurality of square gate blocks having a plurality of logic gates arranged in an array. A signal source node is connected via respective input signal nodes of the gate blocks to the logic gates in the gate blocks through the respective signal paths having the phase compensation sections.
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Driscoll Benjamin D.
NEC Corporation
Westin Edward P.
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