Semiconductor integrated circuit having pads layout for...

Details Semiconductor integrated circuit having pads layout for... Semiconductor integrated circuit having pads layout for...

2005-12-13

2005-12-13

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S672000, C257S692000, C257S695000, C257S735000

Reexamination Certificate

active

06975020

ABSTRACT:
A semiconductor integrated circuit device includes a semiconductor chip having a memory cell array region surrounded with a peripheral circuit region and includes a plurality of bonding pads disposed at least in one row on only one side of the semiconductor chip. The circuit device may include first leads group disposed adjacent to the bonding pad side and a second leads group disposed opposite the first leads group. The second leads group may be formed over a portion of the semiconductor chip (lead-on-chip structure). A plurality of bonding wires connect the first and second leads group with the plurality of bonding pads respectively.

REFERENCES:
patent: 5446317 (1995-08-01), Sato et al.
patent: 5962926 (1999-10-01), Torres et al.
patent: 6121681 (2000-09-01), Tanaka et al.
patent: 6291898 (2001-09-01), Yeh et al.
patent: 6323545 (2001-11-01), Michii
patent: 6433421 (2002-08-01), Tamaki et al.
patent: 6469327 (2002-10-01), Yasuda et al.
patent: 6476467 (2002-11-01), Nakamura et al.
patent: 6492667 (2002-12-01), Kamiya

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit having pads layout for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit having pads layout for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit having pads layout for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3521930