Semiconductor integrated circuit having multi-level...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

11019922

ABSTRACT:
A computer-aided design method of an integrated circuit includes: calculating current dissipation consumed by logic elements, in a ladder network embracing a plurality of current paths connected between subject first- and second-potential-level power supply wiring; analyzing a tolerable electro-migration current of the subject first-potential-level power supply wiring; analyzing an interval voltage drop between a control point and a specific position on the subject first-potential-level power supply wiring; and comparing a summation of through-currents flowing the logic elements from the control point to the specific point, with the tolerable electro-migration current, and comparing the interval voltage drop with a tolerable voltage drop to determine an optimum location of a via configured to supply power from the subject first-potential-level power supply wiring to the logic elements.

REFERENCES:
patent: 5404310 (1995-04-01), Mitsuhashi
patent: 5537328 (1996-07-01), Ito
patent: 6058257 (2000-05-01), Nojima
patent: 6405354 (2002-06-01), Itazu et al.
patent: 6675139 (2004-01-01), Jetton et al.
patent: 6794674 (2004-09-01), Kusumoto
patent: 7016794 (2006-03-01), Schultz
patent: 7155684 (2006-12-01), Kusumoto
patent: 2002-151592 (2002-05-01), None

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