Semiconductor integrated circuit having macro cells and...

Details Semiconductor integrated circuit having macro cells and... Semiconductor integrated circuit having macro cells and...

2002-06-28

2004-07-13

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06763511

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a designing method of the same, and more particularly to a semiconductor integrated circuit having macro cells and a designing method of the same.
2. Description of the Related Art
In recent years, attention has been paid to a system LSI with a plurality of macro cells on a semiconductor chip, having functions of a central processing unit (CPU), memory devices (ROM, RAM), buffer, peripheral devices that perform various kinds of signal processing, etc.
Since the system LSI comprises the plurality of macro cells, the circuit scale is so large that the direct circuit design for a transistor level cannot be achieved in actuality. For this reason, the system LSI is generally designed in such a manner that a system design, function design, specific logic design and circuit design are sequentially carried out stepwise.
In the system design, each of CPU, ROM, RAM, buffer, the plurality of peripheral devices is provided as one function block, and the operation and structure of the entire system are decided to obtain a desired function. In the function design, the relationship among the respective function blocks and the internal operations of the respective function blocks are decided based on the specification decided by the system design. In the specific logic design, the layout of macro cells for configuring the respective blocks whose internal operations are decided by the function design is performed on the semiconductor chip, and these macro cells are mutually wired (layout wiring) so as to generate a simulation model for a semiconductor integrated circuit. In the circuit design, an electric circuit for a transistor level and the characteristics of devices are decided to satisfy the circuit specification, which is based on the logic design having the function design and the specific logic design.
Here, the macro cells are composed of basic logic devices such as an inverter, a NAND gate, a NOR gate, etc., and basic logic circuits such as a latch, a counter, a memory, etc. formed by combining a plurality of basic logic devices. The macro cells are registered to a memory (library) of a CAD (Computer Aided Design) and the like where the respective functions are described using a programming language such as a hardware description language (HDL), C language (trade name), etc. Data of the simulation model for a semiconductor integrated circuit generated as mentioned above is complied with data of macro cells stored in the memory, thereafter a simulation for an operation is carried out to verify whether or not a desired function is obtained.
FIG. 17
is a top view showing a macro cell of the memory (hereinafter referred to as memory macro) that forms a cell base IC designed by the design method (logic design) of the conventional semiconductor integrated circuit and the peripheral portion thereof. The memory macro has a multi-layer wiring structure. In this example, the explanation is given on the assumption that a three-layer wiring is used.
At an outer edge of a core section
1
, the memory macro has a plurality of signal input/output terminals
2
, power lead-in ground terminals
3
a
11
,
3
a
12
,
3
b
11
and
3
b
12
, and power lead-in power terminals
3
a
21
,
3
a
22
,
3
b
21
and
3
b
22
.
The power lead-in ground terminals
3
a
11
and
3
a
12
, and the power lead-in power terminals
3
a
21
and
3
a
22
are formed by the wiring of second layer, and the power lead-in ground terminals
3
b
11
and
3
b
12
, and the power lead-in power terminals
3
b
21
and
3
b
22
are formed by the wiring of the third layer.
A portion enclosed with a broken line provided at an outside of the core section
1
indicates a region where the memory macro is present, and is called a macro outer frame
4
. In an interior of the core section
1
, a ground terminal
5
a
1
, a power terminal
5
b
1
, a ground terminal
5
a
2
and a power terminal
5
b
2
are formed with a predetermined interval in a vertical direction of the figure. The ground terminals
5
a
1
and
5
a
2
and the power terminals
5
b
1
and
5
b
2
are formed by the wiring of the fourth layer, and connected to wiring to be connected to the ground and wiring to be connected to the power among wiring of the third layer, respectively.
Orbital power rings
6
and
7
are formed double at the outside of the macro outer frame
4
to surround the macro outer frame
4
. The orbital power ring
6
includes horizontal ground wiring
6
a
1
and
6
a
2
and vertical ground lines
6
b
1
and
6
b
2
. The horizontal ground wiring
6
a
1
and
6
a
2
are formed by the wiring of the third layer, and the vertical ground lines
6
b
1
and
6
b
2
are formed by the wiring of the second layer.
The orbital power ring
7
formed in the vicinity of the outer periphery of the orbital power ring
6
includes horizontal ground wiring
7
a
1
and
7
a
2
and vertical power lines
7
b
1
and
7
b
2
. The horizontal power wiring
7
a
1
and
7
a
2
are formed by the wiring of the third layer, and the vertical power lines
7
b
1
and
7
b
2
are formed by the wiring of the second layer.
The power lead-in ground terminals
3
a
11
and
3
a
21
are connected to power lead-in ground lines
8
a
11
and
8
a
21
, which are formed by the wiring of the second layer, respectively. Similarly, the power lead-in ground terminals
3
a
12
and
3
a
22
, are connected to power lead-in ground lines
8
a
12
and
8
a
22
, which are formed by the wiring of the second layer, respectively.
The power lead-in ground terminals
3
b
11
and
3
b
21
, are connected to power lead-in ground lines
8
b
11
and
8
b
21
, which are formed by the wiring of the third layer, respectively. The power lead-in ground terminals
3
b
12
and
3
b
22
, are connected to power lead-in ground lines
8
b
12
and
8
b
22
, which are formed by the wiring of the third layer, respectively.
The power lead-in ground lines
8
a
11
and
8
a
12
are connected to the horizontal ground wiring
6
a
1
and
6
a
2
through via holes, respectively, and the power lead-in ground lines
8
a
21
and
8
a
22
are connected to the horizontal power wiring
7
a
1
and
7
a
2
through via holes, respectively.
The power lead-in ground lines
8
b
11
and
8
b
12
are connected to the vertical ground lines
6
b
1
and
6
b
2
through via holes, respectively, and the power lead-in ground lines
8
b
21
and
8
b
22
are connected to the vertical power lines
7
b
1
and
7
b
2
through via holes, respectively.
The horizontal power ground lines
6
a
1
and the horizontal power wring
7
a
1
are connected to a vertical ground bus
9
a
and a horizontal power bus
9
b
, which are formed by the wring of the fourth layer, through via holes, respectively.
As illustrated in
FIG. 18
, the vertical power bus
9
a
is connected to the horizontal ground wiring
6
a
2
, which constitutes the orbital power ring
6
formed to enclose the macro outer frame
4
, through a via hole. Similarly, the vertical power bus
9
b
is connected to the horizontal power wiring
7
a
2
, which constitutes the orbital power ring
7
formed to enclose the macro outer frame
4
, through a via hole.
The vertical ground line
6
b
2
is connected to a horizontal ground bus
10
a
formed in the first layer through a via hole, and the vertical power line
7
b
2
is connected to a horizontal power bus
10
b
formed in the first layer through a via hole. The horizontal ground bus
10
a
is connected to the vertical ground line
6
b
1
, which constitutes the orbital power ring
6
formed to enclose the macro outer frame
4
, through a via hole. The horizontal power bus
10
b
is connected to the vertical power line
6
b
1
, which constitutes the orbital power ring
7
formed to enclose the macro outer frame
4
, through a via hole.
In this way, the orbital power rings
6
and
7
are formed to enclose the macro outer frame
4
for each macro cell, and a current is supplied to the macro cell from the corresponding orbital ring.
Moreover, if a horizont

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