Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2001-02-28
2002-08-20
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S093000, C326S098000
Reexamination Certificate
active
06437603
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in Japanese Patent Application No. H12-53674 filed on Feb. 29, 2000 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit such as a processor, and especially, it relates to a semiconductor integrated circuit having a keeper circuit holding a signal indicative of a logical operation result.
2. Related Background Art
A node which is called a dynamic node whose logic dynamically changes in response to logic of an input signal exists inside a semiconductor integrated circuit. It is often the case that a keeper circuit is connected to this kind of node in order to avoid an unintentional change in the logic.
FIG. 1
is a circuit diagram showing a prior art keeper circuit and illustrates an example of constituting the keeper circuit by a PMOS transistor Q
51
. The keeper circuit shown in
FIG. 1
is connected to input/output terminals of an inverter IV
51
, and an input of the inverter IV
51
is maintained at a high level when an output of the inverter IV
51
turns to a low level.
In the circuit shown in
FIG. 1
, however, since the PMOS transistor Q
51
tries to maintain the high level when the input of the inverter IV
51
is changed from the high level to the low level, and hence it disadvantageously takes time until the output logic of the inverter IV
51
turns to the low level. Further, when the drive capability of the PMOS transistor Q
51
is sufficiently large, the output logic of the inverter IV
51
may not turn to the low level.
On the other hand,
FIG. 2
is a circuit diagram showing a convention example in which a keeper circuit consisting of PMOS transistors Q
52
and Q
53
is connected to output terminals of NOR operation circuits
51
and
52
, and this is a circuit diagram disclosed in
FIG. 6
of Japanese Patent Application Laid-open No. 166216/1997. The PMOS transistors Q
52
and Q
53
shown in
FIG. 2
are connected between input/output terminals of inverters IV
52
and IV
53
. When the outputs of the inverters IV
52
and IV
53
turn to the low level, the PMOS transistors Q
52
and Q
53
are turned on to maintain inputs of the inverters IV
52
and IV
53
on the high level.
The circuit shown in
FIG. 2
also has such a problem as that it takes a long time to change a logic of output signals from the inverters IV
52
and IV
53
when the logic of the input signal has varied, as similar to the circuit illustrated in FIG.
1
. Furthermore, when the drive capability of the PMOS transistors Q
52
and Q
53
is too large, the logic of output signals from the inverters IV
52
and IV
53
may not change even if the logic of the input signal has varies.
On the other hand,
FIG. 3
is a circuit diagram presented in ISSCC'98 (“A 1.0 GHz Single-Issure 64 bit Power PC Integer Processor” J. Silberman, et. al, IBM Austin Research Lab. ISSCC Session FP 15.1, Slide Supplement).
The circuit shown in
FIG. 3
is different from the circuit of
FIG. 2
in that a PMOS transistor Q
54
and an NMOS transistor Q
55
which are connected in series are newly provided at rear stages of NOR operation circuits
51
and
52
instead of the NAND gates G
51
and G
52
.
The circuit shown in
FIG. 3
is also provided with a keeper circuit consisting of the PMOS transistor Q
52
, and has the same problem as that of the circuit of FIG.
2
.
On the other hand,
FIG. 4
is a circuit diagram of a dual rail which outputs a result of an NOR operation and a result of an NAND operation carried out between two input signals. The circuit shown in
FIG. 4
includes two NMOS transistors Q
56
and Q
57
which are connected to each other in parallel to execute the NOR operation, two NMOS transistors Q
58
and Q
59
which are connected to each other in series to execute the NAND operation, and PMOS transistors Q
60
and Q
61
which are connected to drain terminals of the transistors Q
56
and Q
57
and a drain terminal of the transistor Q
58
and cross-multiplied to each other.
The PMOS transistors Q
60
and Q
61
acts as keeper circuits which prevent fluctuations in each drain voltage of the transistors Q
56
, Q
57
and Q
58
.
In the circuit shown in
FIG. 4
, however, when the logic of an input signal is changed and each drain voltage of the transistors Q
56
, Q
57
and Q
58
is thereby about to vary, the PMOS transistors Q
60
and Q
61
operate so as to prevent the change of each drain voltage, and hence it disadvantageously takes time to change the logic of an output signal. Further, if the drive capability of the PMOS transistors Q
60
and Q
61
is high, the output logic may not change.
On the other hand,
FIG. 5
is a circuit diagram showing a semiconductor integrated circuit having a latch load circuit
53
for holding a signal indicative of a result of the NOR operation and a signal indicative of a result of the NAND operation, these arithmetic operations being executed between two input signals.
The latch load circuit
53
shown in
FIG. 5
includes transistors Q
60
and Q
62
connected in series between a power supply terminal and a drain terminal of the transistor Q
57
, transistors Q
61
and Q
63
connected in series between the power supply terminal and a drain terminal of the transistor Q
58
, and a transistor Q
64
connected between source terminals of the transistors Q
62
and Q
63
.
The transistors Q
60
and Q
61
are cross-multiplied to each other, and the transistors Q
62
and Q
63
are also cross-multiplied to each other.
The NOR operation result of the input signals is outputted from a connection point CN
1
between the transistor Q
60
and the transistor Q
62
, and the NAND operation result of the input signals is outputted from a connection point CN
2
between the transistor Q
61
and the transistor Q
63
. A transistor for pre-charge is connected to each of the connection points CN
1
and CN
2
.
The latch load circuit
53
latches drain voltages of the transistors Q
60
and Q
62
and drain voltages of the transistors Q
61
and Q
63
by using an edge of a clock signal CLK. The semiconductor integrated circuit shown in
FIG. 5
outputs differential signals each of which has the logic different from each other.
The semiconductor integrated circuit shown in
FIG. 5
, however, constantly outputs differential signals even if only one of the logic is utilized, which leads to a problem of increase in the circuit scale. Furthermore, when the semiconductor integrated circuit shown in
FIG. 5
is used only when the differential signals are required, the application range is narrowed, thereby lowering the utility value.
SUMMARY OF THE INVENTION
In view of the above-described problems in the prior art, it is an object of the present invention to provide a semiconductor integrated circuit capable of stable operating at high speed.
To achieve this object, according to the present invention, there is provided a semiconductor integrated circuit having a logical operation function, comprising:
at least three of first logic operating means configured to output the results of different logic operations executed with respect to a plurality of input signals, any one of said at least three of first logic operating means outputting a signal having first logic in accordance with logic of said plurality of input signals; and
a plurality of keeper circuits which are provided respectively corresponding to said at least three of first logic operating means and can maintain an output voltage of said corresponding first logic operating means at a voltage in accordance with second logic,
wherein each of said plurality of keeper circuits forcibly sets an output from said corresponding logic arithmetic operating means to said second logic when an output from said first logic operating means other than said corresponding first logic operating means is said first logic.
According to the present invention, when the output logic of any f
Gray Cary Ware & Freidenrich LLP
Kabushiki Kaisha Toshiba
Tan Vibol
Tokar Michael
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