Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2011-05-17
2011-05-17
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C327S208000
Reexamination Certificate
active
07944242
ABSTRACT:
A semiconductor integrated circuit includes a multiplexer, a signal generating circuit, a control circuit, m inverters, n two-input NOR circuits, and cascade connected n two-shift registers. The control circuit generates a control signal in the disable state in a normal operation in which the clock signal is supplied. The control circuit generates a control signal in an enable state in the other-than-normal operation in which a higher voltage source voltage is supplied while the clock signal is not supplied. The multiplexer receives the clock signal and a low-frequency signal outputted from the signal generating circuit. The multiplexer supplies the clock signal to the sequence of the inverters upon receipt of the control signal in the disable state, and supplies the low-frequency signal to the sequence of the inverters upon receipt of the control signal in the enable state.
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Hojo Takehiko
Wada Masaharu
Kabushiki Kaisha Toshiba
Tan Vibol
Turocy & Watson LLP
White Dylan
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