Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-09-05
2006-09-05
Lane, Jack A. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C714S051000, C714S055000
Reexamination Certificate
active
07103738
ABSTRACT:
A backup memory, a DMA (direct memory access) controller, and a WDT (watch dog timer) are provided in addition to a CPU (central processing unit), a RAM (random access memory), and a peripheral circuit. The DMA controller exercises control so that respective data of the CPU, RAM and peripheral circuit is saved in the backup memory each time the CPU, being under normal operation, supplies a counter reset signal to the WDT, and so that the data that has been saved in the backup memory is restored to the CPU, the RAM and the peripheral circuit, respectively, if the WDT has detected a program runaway and outputted a time-over signal. Therefore, even in a case where a program runaway has occurred in the CPU, normal operation is permitted to be resumed from midway in the program.
REFERENCES:
patent: 6-131218 (1994-05-01), None
Benno Hiroshi
Kamiyoshi Tsutomu
Uenishi Tsuneo
Yoneda Takashi
Yoshioka Shirou
Lane Jack A.
McDermott Will & Emery LLP
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