Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2001-05-16
2004-12-14
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S027000, C326S081000, C326S031000, C327S534000
Reexamination Certificate
active
06831483
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, a method of designing the same, a program recording medium on which a program for supporting designing of the semiconductor integrated circuit is recorded, and a design data recording medium on which design data used for designing the semiconductor integrated circuit is recorded. More particularly, the invention relates to a technique effective for use in a semiconductor integrated circuit suitable for high-speed and low-power operation.
In recent years, a semiconductor integrated circuit device is requested to have improved operating frequency and lower power consumption. In order to improve the operating frequency, generally, the threshold voltage of an insulated gate field effect transistor (hereinbelow, simply called an MIS (Metal Insulated Semiconductor) transistor or a MOS (Metal Oxide Semiconductor) transistor) used in a semiconductor integrated circuit is decreased. When the threshold voltage is set to too low, however, a MOS transistor cannot be completely turned off due to a subthreshold characteristic of the MOS transistor, a subthreshold leak current increases, and a problem such that power consumption of the semiconductor integrated circuit becomes very high occurs. For solving the problem, Japanese Unexamined Patent Publication No. Hei 11(1999)-195976 (first literature) discloses a method of preparing a plurality of kinds of MOS transistors having different threshold voltages and selectively using the MOS transistors in accordance with the degree of timing allowance of a signal path in a semiconductor integrated circuit.
To address the request for reduction in power consumption, Japanese Unexamined Patent Publication No. Hei 10(1998)-189749 (U.S. Pat. No. 6,097,043) (second literature) discloses a method of preparing a plurality of power supply voltages and selectively using a circuit for supplying a high voltage and a circuit for supplying a low voltage, thereby reducing the power.
The method disclosed in the first literature intends to achieve both improvement in operating speed and reduction in leak current in the standby mode by applying a circuit using a MOS transistor of a low threshold voltage to a path having no timing allowance (critical path) and applying a circuit using a MOS transistor having a high threshold voltage to other paths. In a circuit to which the technique is applied, however, when an attempt is made to reduce the power consumption in active operation by decreasing the power supply voltage, the threshold voltage of a MOS transistor has to be also decreased to maintain the operating speed. It was clarified by the examination of the inventors of the present invention that large reduction in power consumption cannot be expected due to the power consumption increased by the leak current in the standby mode.
According to the method disclosed in the second literature, a plurality of power supply voltages are prepared in a semiconductor integrated circuit. By supplying a high voltage to a circuit as a component of a path having no allowance (critical path) and supplying a low voltage to a circuit as a component of a path having an allowance in accordance with the degree of timing allowance of a signal path, the method intends to achieve improved operating speed and reduction in power in active operation. Regarding a circuit to which the technique is applied, however, the inventors of the present invention have uncovered that since a substrate voltage in a MOS transistor to which a high operating voltage is supplied and that in a MOS transistor to which a low operating voltage is supplied are different from each other, an isolating region is necessary in the substrate, and the chip area may increase. Since all of MOS transistors have the same threshold voltage, there is the possibility that power consumption increases due to a leak current in the standby mode.
SUMMARY OF THE INVENTION
An object of the invention is to provide a semiconductor integrated circuit realizing high-speed and lower-power operation from the viewpoint of operating power source voltage and substrate bias voltage.
Another object of the invention is to provide a semiconductor integrated circuit without an overhead area, realizing improved operating speed, reduced power consumption in an active mode, and reduced power consumption in a standby mode.
Another object of the invention is to provide a designing method suitable for designing a semiconductor integrated circuit without an overhead area, realizing improved operating speed, reduced power consumption in an active mode, and reduced power consumption in a standby mode. Further another object of the invention is to provide a program recording medium on which a design supporting program suitable for increasing efficiency in designing such a semiconductor integrated circuit is recorded and, further, a design data recording medium on which design data suitable for increasing efficiency in designing such a semiconductor integrated circuit is recorded.
The above and other objects and novel features of the invention will become apparent from the description of the specification and the accompanying drawings.
An embodiment of the invention disclosed in the application will be briefly described as follows.
1. <Sharing of Substrate Potential>
From the viewpoint of sharing a substrate potential by logic gates of different operation power sources, a semiconductor integrated circuit has: a first logic gate (
1
) using, as an operation power source, a first pair of potentials (VDDL and VSSL or VDDL and VSS) having a relatively small potential difference; and a second logic gate (
2
) using, as an operation power source, a second pair of potentials (VDDH and VSSH or VDDH and VSS) having a relatively large potential difference. Each of the first and second logic gates has an MIS transistor, and substrate potentials (VBP and VBN, or VDDH and VSSH) of the MIS transistors are commonly used by the first and second logic gates.
Since the second logic gate has a larger potential difference of the operation power source as compared with the first logic gate, an output voltage amplitude by the MIS transistors (MP
0
and MN
0
) of the second logic gate is larger than that of the MIS transistors (MP
1
and MN
1
) of the first logic gate. The second logic gate has a relatively higher driving capability and operates at high speed. Since the power consumption in logic operation is proportional to the square of the output voltage amplitude, the first logic gate
1
can operate with less power. At this time, the MIS transistor has a characteristic such that the threshold voltage increases due to a reverse substrate bias applied across the source and the substrate, and the threshold voltage decreases by a forward substrate bias. Since the substrate potentials of the MIS transistors are commonly used by the first and second logic gates, even in the case of generating different substrate bias states in the first and second logic gates, MOS transistors as components of the logic gates can be formed in the common well region. When the substrate potential of the first logic gate and that of the second logic gate are made different from each other, even the conduction type of the MIS transistors is the same, the well regions have to be electrically isolated from each other, and the chip occupying area enlarges due to the isolation areas. The substrate bias states in the first and second logic gates can be set according to the level of the substrate potential and that of the power source potentials of both of the logic circuits. When the forward substrate bias is applied to an MIS transistor included in the second logic gate intended for high speed operation, the threshold voltage decreases, and the operation can be performed at higher speed. On the other hand, when the reverse substrate bias is applied to an MIS transistor included in the first logic gate intended for low power operation, the threshold voltage increases, the subthreshold leak current at the tim
Ichihashi Motoi
Shimazaki Yasuhisa
Chang Daniel
Miles & Stockbridge P.C.
Renesas Technology Corp.
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