Semiconductor integrated circuit having DRAM mounted on semicond

Details Semiconductor integrated circuit having DRAM mounted on semicond Semiconductor integrated circuit having DRAM mounted on semicond

1998-02-25

1999-08-03

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Data refresh

3652385, G11C 11406

Patent

active

059333812

ABSTRACT:
In a semiconductor integrated circuit, a CPU (2), a DRAM (3), and a bus controller (5) are mounted on a same semiconductor chip. The bus controller (5) has a refresh control circuit (7, 70) including a refresh request circuit to output a refresh request at a constant timing, a forced refresh request circuit to output the refresh request at an optional timing that is different from the constant timing, and a refresh request stop circuit to output the refresh request forcibly.

REFERENCES:
patent: 4172282 (1979-10-01), Aichelmann, Jr. et al.
patent: 4701843 (1987-10-01), Cohen
patent: 5345574 (1994-09-01), Sakurada et al.
patent: 5379400 (1995-01-01), Barakat et al.
patent: 5717644 (1998-02-01), Hadderman et al.

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