Excavating
Patent
1997-06-25
1999-01-26
DeCady, Albert
Excavating
371 271, G01R 3128
Patent
active
058645659
ABSTRACT:
A semiconductor integrated circuit and method for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits.
REFERENCES:
patent: 4517661 (1985-05-01), Graf et al.
patent: 4760330 (1988-07-01), Lias, Jr.
patent: 4794597 (1988-12-01), Ooba et al.
patent: 4799004 (1989-01-01), Mori
patent: 4827476 (1989-05-01), Garcia
patent: 4837765 (1989-06-01), Suzuki
patent: 4860259 (1989-08-01), Tobita
patent: 4864579 (1989-09-01), Kishida et al.
patent: 4879717 (1989-11-01), Sauerwald et al.
patent: 4916700 (1990-04-01), Ito et al.
patent: 4926426 (1990-05-01), Scheuneman et al.
patent: 5305261 (1994-04-01), Furutani et al.
patent: 5422892 (1995-06-01), Hii et al.
patent: 5457696 (1995-10-01), Toshiki
Cowan Gregory L.
Ochoa Roland
Pierce Kim M.
De'cady Albert
Micro)n Technology, Inc.
LandOfFree
Semiconductor integrated circuit having compression circuitry fo does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit having compression circuitry fo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit having compression circuitry fo will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1455583