Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-11-29
2002-10-15
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S203000
Reexamination Certificate
active
06466496
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrate circuits and memory processing systems, and more particularly to structures for high-speed data transfer.
2. Description of the Background Art
Double data rate synchronous dynamic random access memories (hereinafter referred to as DDR-SDRAMS) employ SSTL2 (SSTL: Stub Series Terminated Transceiver Logic), which is standardized by JEDEC (Joint Electron Device Engineering Council), as an interface for data transfer.
SSTL2 is based on termination. SSTL2 has two types of data transfer scheme: in one data transfer scheme, a transmission line is terminated only at one end (SSTL2 class 1) and in another, a transmission line is terminated at both ends (SSTL2 class 2). In conventional DDR-SDRAMs, SSTL2 class 2 has been employed where the transmission line is terminated at both ends.
With the conventional data transfer scheme, however, a problem rises at the implementation in a server. A first problem in the conventional DDR-SDRAM will be described with reference to FIG.
18
.
FIG. 18
shows the relation between memory modules
900
A,
900
B and
900
C and a system controller
902
transmitting/receiving signals to/from the memory modules. The memory modules and system controller
902
are mounted on a main board not shown.
DDR-SDRAM is mounted on a module substrate constituting the memory module. Each DDR-SDRAM is responsive to a control signal sent from system controller
902
to supply stored data to system controller
902
as an output. The data is transferred to system controller
902
via data transmission lines
90
a
,
90
b
, . . . ,
90
m
. In addition, the memory module receives data from system controller
902
via data transmission lines
90
a
~
90
m
and stores the data. System controller
902
and memory modules receive an external clock signal EXTCLK determining an operation timing from a clock generator not shown.
Data transmission lines
90
a
~
90
m
, being SSTL2 class 2 described above, are terminated at both ends, that is, at the side of system controller
902
and at the side opposite to system controller
902
. As an example of a termination technique, a case where resistance elements R
1
and R
2
are employed will be described. Resistance elements R
1
and R
2
are connected between a node receiving a power supply voltage Vtt and an end of the data transmission line.
As shown in the figure, when the data transmission lines are gathered around system controller
902
, the area around system controller
902
becomes excessively congested with the termination elements of the data transmission lines. Here, as the amount of data to be processed increases, the implementation becomes more difficult.
A second problem in the conventional DDR-SDRAM will be described with reference to FIG.
19
.
FIG. 19
shows the relation between a memory chip and an impedance in a data transmission line
90
. Memory modules are electrically connected to data transmission line
90
at nodes ne, nf, ng, . . . , respectively. In
FIG. 19
, a memory chip
910
included in memory module
900
A is shown as a representative.
Memory chip
910
includes a DLL (delayed locked loop) circuit
920
generating an internal clock signal for determining the timing of internal operations according to an external clock signal, a data output buffer
930
for externally supplying data as an output and a data input buffer
940
for taking in data received from system controller
920
. Symbol CLK represents a clock pin taking in the external clock signal and DQS represents a pin corresponding to a data strobe signal determining the timing of input/output of data.
Here, let Z
0
represent a characteristic impedance of a data transmission line (between system controller
902
and node ne) as a reference, L
0
a characteristic inductance, and C
0
a characteristic capacitance. Impedance Z
0
can be represented by the expression (1). Assume that the input capacitance is Cin and the memory module is implemented with a predetermined pitch Pitch, the impedance at node
nf lowers from Z
0
to Z
1
. Impedance Z
1
is represented by the expression (2).
Z0
=
L0
C0
(
1
)
Z1
=
L0
C0
+
Cin
Pitch
(
2
)
Thus the particular problem exists at the time of implementation that the impedance changes with the arrangement of memory chips memory modules). This effect is more apparent in a commonly-employed memory expansion technique where the memory is expanded later.
With reference to
FIG. 20
, an example where module substrates are mounted at different positions on the main board from each other will be described. In an A type mounting, for example, data arrives at system controller
902
in approximately the same phase with external clock signal EXTCLK (at time t
1
). On the other hand, in a B type mounting, data arrival at system controller
902
(at time t
2
) lags the external clock signal EXTCLK. Further, in a C type mounting, data arrives system controller
902
(at time t
0
) earlier than external clock signal EXTCLK and data receipt completes (at time t
3
) earliest among three exemplary types of mounting. Thus, the difference in the timing of data arrival stems from the change in impedance depending on the type of mounting.
Now, to accommodate the memory expansion in the future, a set up time of system controller
902
is set to (t
2
~tx) and a hold time is set to (tx~t
3
) (here, t
2
<tx<t
3
). This setting allows the device to be applied to any types of mounting of memories.
When the set up time/hold time are to be set such that they are applicable to any types of mounting, the set up time and hold time inevitably becomes short. In an actual 133 MHz DDR-SDRAM, the set up time/hold time is too short, and together amounts only 1000×10
−12
seconds (1000 pico seconds).
As can be seen from the above, it has been difficult to secure sufficient set up time/hold time which are important parameters for data transfer in the structure of the conventional memory processing system.
SUMMARY OF THE INVENTION
Thus, the present invention provides a memory processing system capable of securing sufficient set up time/hold time allowing the memory expansion and the high-speed processing.
A memory processing system according to one aspect of the present invention includes: a plurality of memory chips; a system controller controlling each of the plurality of memory chips; and a data transmission line for transferring data between the system controller and the plurality of memory chips; each of the plurality of memory chips including a test circuit responsive to a request from the system controller to perform a test for measuring data transmission distance of the data transmission line to the system controller, the system controller determining for each of the plurality of memory chips a set up time/hold time for receiving the data based on the measurement result at the test circuit.
According to the memory processing system described above, the set up time/hold time can be determined independently for each memory chip. Then, the ratio of set up time/hold time becomes larger in the memory processing system according to the present invention than in the conventional system. In other words, the set up time/hold time, which serves as an important parameter for data transfer, can be sufficiently secured. Therefore, high-speed data transfer can be achieved regardless of the type of mounting and subsequent memory expansion.
Preferably in. the memory processing system, termination is made only at one end opposite to the side of the system controller. Hence, the line length can be made equal in compliance with JEDEC standard through line folding and so on utilizing the region at the side of the system controller where the termination elements have conventionally been arranged.
Preferably, the memory processing system monitors the reflected wave of an output signal. Then, the length of the data transmission line can be measured based on the change in potential of the data transmission line.
Particularly, the memory processin
Elms Richard
McDermott & Will & Emery
Phung Anh
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