Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2001-08-29
2003-02-11
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S068000, C326S083000, C326S080000
Reexamination Certificate
active
06518790
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit having a circuit configuration for transmitting complementary signals.
2. Description of the Background Art
In an LSI (Large-Scale Integration), there is a case where a power supply voltage of an input/output buffer for transmitting/receiving a signal to/from the outside is different from that of an internal circuit for processing the signal. More specifically, there is a case where a high voltage is applied to the input/output buffer and a low voltage is applied to the internal circuit.
By setting the voltage supplied to the internal circuit to a low value, the following effects can be obtained. First, power consumption in the internal circuit can be suppressed. Second, when the voltage is lowered, an issue of a withstand voltage in a gate electrode of a transistor can be lightened. Consequently, the thickness of a gate oxide film in a transistor as a component of the internal circuit can be reduced. Third, by reducing the thickness of the gate oxide film, it is expected to increase the operating speed of the internal circuit.
In the case of supplying a high voltage to the input/output buffer and a low voltage to the internal circuit, a transistor having a thick gate oxide film has to be used for the input/output buffer and a transistor having a thin gate oxide film has to be used for a thin gate oxide film. At the time of supplying a signal to the internal circuit, the voltage of the signal has to be changed.
The configuration of the main portion of a conventional semiconductor integrated circuit will now be described with reference to FIG.
8
. In the following, a CMOS (Complementary Metal-Oxide Semiconductor) LSI in which a power supply voltage at an input stage is 3.3 V and a power supply voltage in an internal circuit is 1.8 V will be described as an example. Each of input and output signals of the internal circuit is set at. a CMOS level.
The conventional semiconductor integrated circuit shown in
FIG. 8
has: voltage transforming circuits
910
and
920
which receive signals IN and /IN complementary to each other supplied from the outside, respectively; and a signal transmitting circuit
900
including CMOS inverters
930
and
940
for inverting outputs of the voltage transforming circuits
910
and
920
, signal lines L
3
and L
4
, and CMOS inverters
950
and
960
for inverting outputs of the inverters
930
and
940
. Outputs of the signal transmitting circuit
900
are supplied to an internal circuit (not shown) operated from a 1.8 V power supply.
The voltage transforming circuits
910
and
920
operate so as to drop the H level of the signals IN and /IN to around 1.8 V. The inverter
930
includes a PMOS transistor
803
and an NMOS transistor
804
each having a gate connected to an output node
801
of the voltage transforming circuit
910
. The transistor
803
is connected between a power supply voltage of 1.8 V and a node 807. The transistor
804
is connected between a ground voltage and the node
807
(signal line L
3
).
The inverter
940
includes a PMOS transistor
805
and an NMOS transistor
806
each having a gate connected to an output node
802
of the voltage transforming circuit
920
. The transistor
805
is connected between a power supply voltage of 1.8 V and a node
808
. The transistor
806
is connected between a ground voltage and the node
808
(signal line L
4
).
The inverter
950
includes a PMOS transistor
811
and an NMOS transistor
812
each having a gate connected to the signal line L
3
. The transistor
811
is connected between a power supply voltage of 1.8 V and a node
115
. The transistor
812
is connected between a ground voltage and the node
115
.
The inverter
960
includes a PMOS transistor
813
and an NMOS transistor
814
each having a gate connected to the signal line L
4
. The transistor
813
is connected between a power supply voltage of 1.8 V and a node
116
. The transistor
814
is connected between a ground voltage and the node
116
.
When the H level of an output of each of the voltage transforming circuits
910
and
920
does not drop to 1.8 V, the output cannot be received by the transistor having the thin gate oxide film. The inverter
930
is therefore constructed by the transistors
803
and
804
adapted to 3.3 V and uses the power supply voltage of 1.8 V. Similarly, the inverter
940
is constructed by the transistors
805
and
806
adapted to 3.3 V and uses the power supply voltage of 1.8 V. On the other hand, a transistor adapted to 1.8 V is used as each of the transistors
811
to
814
. To an internal circuit (not shown), signals of the nodes
115
and
116
are supplied.
The circuit configuration, however, has the following problems. When a deviation occurs between complementary signals, the deviation cannot be compensated by the cascaded configuration of the inverters.
The drivability of the transistor for 3.3 V is low (particularly, the drivability of a PMOS transistor is lower than that of an NMOS transistor). In order to raise the drivability, it is therefore necessary to widen the gate width of the transistor. When the drivability is compensated by the gate width, the gate width of the transistor is widened. It accordingly increases layout area and parasitic capacitance.
Generally, a transistor having high withstand voltage has a high threshold voltage relative to the withstand voltage. Specifically, a transistor for 3.3 V has a threshold voltage higher than that of a transistor for 1.8 V. An operating current (source-drain current) of a MOS transistor depends on a difference (Vgs−Vt) between a gate-source voltage Vgs and a threshold voltage Vt.
In inverters
930
and
940
constructed by the transistors for 3.3 V but driven on the source voltage of 1.8 V, therefore, the operating current of each of the MOS transistors cannot be sufficiently obtained. As a result, it deteriorates the operating speed of signal transmitting circuit
900
.
As the amplitude of an output signal required by signal transmitting circuit
900
, that is, the source voltage (1.8 V) of an internal circuit decreases, the more the problem becomes conspicuous. Particularly, when the source voltage of the internal circuit becomes lower than the threshold voltage of the transistors for 3.3 V for receiving outputs of voltage transforming circuits
910
and
920
at the front stage, signal transmitting circuit
900
becomes inoperable.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor integrated circuit having a circuit capable of transmitting complementary signals at optimum timings without enlarging a layout area.
The present invention also provides a semiconductor integrated circuit having a circuit for changing the voltage amplitude of an input signal at high speed.
A semiconductor integrated circuit according to the present invention comprises: a first signal line for transmitting a first signal; a second signal line for transmitting a second signal substantially complementary to the first signal; first and second MOS transistors cross coupled between the first and second signal lines; a first logic gate including a third MOS transistor which receives a signal of the first signal line by its gate; and a second logic gate including a fourth MOS transistor which receives a signal of the second signal line by its gate.
Preferably, the semiconductor integrated circuit further has: a first terminal for receiving the first signal; a second terminal for receiving the second signal; a third logic gate including a fifth MOS transistor which is connected between the first terminal and the first signal line and is formed under process parameters different from those of the first to fourth MOS transistors; and a fourth logic gate including a sixth MOS transistor which is connected between the second terminal and the second signal line and is formed under process parameters different from those of the first to fourth MOS
Kondoh Harufusa
Wada Yoshiki
Mitsubishi Denki & Kabushiki Kaisha
Tokar Michael
Tran Anh
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