Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2002-12-10
2004-10-26
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S086000, C365S189110
Reexamination Certificate
active
06809554
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-275561, filed Sep. 20, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit having a voltage level conversion circuit and at least two types of logic circuit elements that operate at power supply voltages having different values.
2. Description of the Related Art
With the trend toward smaller semiconductor integrated circuits, in order to ensure the reliability of internal circuit elements and reduce the power consumption it is preferable to decrease the supply voltage. At a low supply voltage, however, an internal circuit cannot be operated at a high speed or a write cannot be sufficiently done in memory cells. The above requirements for reliability and low power consumption can be achieved by applying a high power supply voltage to a necessary portion of a semiconductor integrated circuit and operating it.
Since power supply voltages having different values are applied to a single semiconductor integrated circuit, and circuits designed to perform logic processing at different signal levels are mounted together, a level conversion circuit for converting signal levels is required between the two circuits.
In a conventional semiconductor integrated circuit including a level conversion circuit, an output signal from a logic circuit to which a lower power supply voltage is applied is input to the level conversion circuit to which two types of power supply voltages, i.e., higher and lower voltages, are applied, the level conversion circuit converts the amplitude of the output signal having a level corresponding to the lower power supply voltage to the amplitude corresponding to the higher power supply voltage, and the resultant voltage signal is output to the circuit that operates at the higher power supply voltage (see, for example, U.S. Pat. No. 6,067,257 (Page 1, FIG. 7)
With the recent trends toward mobile electronic devices, a specified voltage may not always be applied to such a semiconductor integrated circuit having different power supply voltage levels when a power supply voltage is applied from a battery exhausted upon discharging or from a charging power supply or a shock, vibration, or the like is given to a power supply circuit including a battery. More specifically, when the higher power supply voltage becomes unstable, the voltage will be lowered to a value lower than that of the lower power supply voltage. Alternatively, the connection terminal of the lower voltage supply may undergo unstable contact, and the power supply may be instantaneously interrupted or stopped.
A fluctuant power supply voltage lower than the minimum level required to determine a logical operation may therefore be applied to a logic circuit element. As a consequence, the logic operation of the logic circuit element becomes unstable. In this case, for example, the conduction state of transistors forming an inverter formed of a CMOS circuit may become unstable, and a leakage current may flow across the power supply terminals of this inverter via the CMOS circuit. As described above, leakage current may flow in various portions of a semiconductor integrated circuit due to unstable power supply voltages, and hence operation errors and increases in power consumption have not been prevented.
A conventional semiconductor integrated circuit including a level conversion circuit will be described below with reference to
FIGS. 8A and 8B
.
FIG. 8A
shows a block diagram of a semiconductor integrated circuit having a level conversion circuit
83
between a logic circuit
81
to which a power supply voltage VL is applied and a logic circuit
82
to which a power supply voltage VH is applied. The power supply voltage VH is higher than the power supply voltage VL.
This semiconductor integrated circuit includes the logic circuit
81
to which the power supply voltage VL is applied and which outputs a signal S
1
having the amplitude corresponding to the power supply voltage VL, the level conversion circuit
83
which is connected to the logic circuit
81
, to which the power supply voltages VL and VH are applied, and which converts the input signal S
1
into a signal S
2
having the amplitude corresponding to the power supply voltage VH and outputs the signal S
2
, and the logic circuit
82
to which the power supply voltage VH is applied and which outputs a signal S
3
having the amplitude corresponding to the power supply voltage VH. A simple logic element (to be referred to as an H·L conversion logic element hereinafter) such as an inverter, NAND circuit, or NOR circuit (not shown) for level-converting the signal S
3
into a signal having the amplitude corresponding to the power supply voltage VL is further connected to the input stage of the logic circuit
81
.
Assume that in this case, the logic circuits
81
and
82
include CMOS inverters which are constituted by PMOS and NMOS transistors and receive input signals at their commonly connected gates.
FIG. 8B
is a circuit diagram showing an example of the level conversion circuit
83
. The level conversion circuit
83
includes a latch circuit. This latch circuit is comprised of PMOS transistors P
84
and P
85
having source terminals to which the power supply voltage VH is applied and gate terminals and drain terminals which are cross-connected to each other, an NMOS transistor N
84
having a drain terminal connected to ground and a source terminal connected to the drain terminal of the PMOS transistor P
84
and the gate terminal of the PMOS transistor P
85
at a node
86
, and an NMOS transistor N
85
having a drain terminal connected to ground and a source terminal connected to the drain terminal of the PMOS transistor P
85
and the gate terminal of the PMOS transistor P
84
at a node
87
.
The level conversion circuit
83
is further comprised of an inverter
88
to which the power supply voltage VL is applied and which has an output terminal to which the gate terminal of the NMOS transistor N
84
and the input terminal of an inverter
89
are connected and outputs the signal obtained by inverting the logic of the input signal S
1
, the inverter
89
which outputs the signal obtained by inverting an input signal from the inverter
88
to the gate terminal of the NMOS transistor N
85
, and an inverter
810
to which the power supply voltage VH is applied and which outputs the signal S
2
obtained by inverting the logic of an input signal from the node
87
.
The operation of the semiconductor integrated circuit including the level conversion circuit
83
shown in
FIGS. 8A and 8B
will be described next.
Conversion (to be referred to as L·H conversion hereinafter) from the signal S
1
having the amplitude corresponding to the power supply voltage VL to the signal S
2
having the amplitude corresponding to the power supply voltage VH will be described first with reference to FIG.
8
B. When the signal S
1
having high level (to be referred to as logic-H hereinafter) of the power supply voltage VL is input to the level conversion circuit
83
, the logic-H signal S
1
is inverted into a signal having low level (to be referred to as logic-L hereinafter) by the inverter
88
. This signal is output to the NMOS transistor N
84
and inverter
89
. The logic-L signal input to the gate terminal of the NMOS transistor N
84
turns off the NMOS transistor N
84
.
The logic-L signal input to the inverter
89
is inverted into a logic-H signal having the amplitude VL. This signal is input to the gate terminal of the NMOS transistor N
85
to turn on the NMOS transistor N
85
. The potential of the node
87
is then pulled down to low level to turn on the PMOS transistor P
84
having the gate terminal to which the potential of the node
87
is input. The potential of the node
86
is set at high level to turn off
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