Semiconductor integrated circuit for preventing deterioration of

Details Semiconductor integrated circuit for preventing deterioration of Semiconductor integrated circuit for preventing deterioration of

1995-05-19

1997-01-28

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

326 9, 326 81, 326121, H03K 1710

Patent

active

055981062

ABSTRACT:
In a semiconductor integrated circuit constructed by thin film transistors (TFTs), an invertor circuit or a NAND circuit is formed by arranging a transmission gate circuit, a P-channel type TFT or an N-channel type TFT between a circuit including at least one P-channel type TFT and a circuit including at least one N-channel type TFT. The N-channel type TFT is earthed. Voltage drop produces by the arranged transmission gate circuit or P-channel or N-channel type TFT, so that the drain voltage of the earthed N-channel type TFT is decreased and an electric field near the drain region of the N-channel type TFT is decreased.

REFERENCES:
patent: 4704547 (1987-11-01), Kirsch
patent: 4857763 (1989-08-01), Sakurai et al.
patent: 5457420 (1995-10-01), Asada

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit for preventing deterioration of does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit for preventing deterioration of, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit for preventing deterioration of will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-943593