Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2001-08-27
2003-03-04
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S100000
Reexamination Certificate
active
06529060
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an input circuit of a semiconductor integrated circuit device. More particularly, the present invention relates to a semiconductor integrated circuit device having a voltage interface circuit (or an input circuit), which converts an input voltage that is higher than a power supply voltage into a voltage that is lower than the power supply voltage.
2. Description of Related Art
The rapid development of semiconductor technology has continuously caused Metal-Oxide-Semiconductor (MOS) integrated circuit devices to become more highly integrated. In a fine structure of the MOS integrated circuit device, the thickness of a gate oxide is as small as 10-14 nm.
To prevent dielectric breakdown of the gate oxide and variation of a threshold voltage due to hot electrons generated during MOS transistor operation, a power supply voltage applied to the fine MOS integrated circuit device is made to be less than the power supply voltage applied to a conventional MOS integrated circuit device.
FIG. 1
illustrates data transfer between semiconductor integrated circuit devices
10
,
12
operating with different power supply voltages (for instance, 3.3 V and 5 V) according to the prior art. Binary data (or a digital signal) outputted to the semiconductor integrated circuit device
12
from the semiconductor integrated circuit device
10
has a low level signal of 0 V and a high level signal of 5 V. Thus, the semiconductor integrated circuit device
12
having the fine structure needs an input circuit to convert the 5 V-input signal to an input signal having an operating voltage or a power supply voltage of the semiconductor integrated circuit device
12
(3.3 V, for example). This input circuit for converting an input voltage is called a “3.3 V to 5 V power interface input circuit” or a “5 V-tolerant input/output circuit.”
The 5 V-tolerant voltage interface circuit of the semiconductor integrated circuit for 3.3 V operation may be accomplished by a manufacturing process or circuit design.
In the former case, a conventional input circuit (for instance, general CMOS inverter) may be applied without modification by using the dual-gate oxide process. This process, however, increases the process cost.
In the latter case, using a single gate oxide thickness, it is possible to solve the aforementioned problem by connecting an N-channel MOS field effect transistor (NMOS transistor) with an input pin, an input terminal, or an input pad, receiving the 5 V-input signal.
FIG. 2
illustrates a circuit diagram of a high voltage interface circuit of a semiconductor integrated circuit device according to the prior art.
The high voltage interface circuit includes a NMOS transistor (MN
1
) having a current path formed between an input pad
14
and an internal logic, and a gate connected to a power supply or operating voltage (VDD), and a PMOS transistor (MP
1
) having a current path formed between the power supply voltage (VDD) and a terminal of the NMOS transistor (MN
1
) connected to the internal logic, and a gate connected to a ground voltage (GND). A voltage higher than the power supply voltage (VDD) applied to the input pad
14
is converted to “VDD-Vthn” (Vthn indicates a threshold voltage of the NMOS transistor) by the NMOS transistor (MN
1
), and the converted voltage is applied to the internal logic.
While a data signal is transferred to the 3.3 V-semiconductor integrated circuit device
12
from the 5 V-semiconductor integrated circuit device
10
in
FIG. 1
, the signal transfer may be temporarily cut off. At this time, the input pad
14
shown in
FIG. 2
comes to a floating condition. If the input pad
14
comes to the floating condition after an initial high level input voltage of 5 V has been applied to it, voltage on the input pad
14
becomes “VDD-Vthn” because the input pad
14
is driven by the PMOS transistor (MP
1
) through the NMOS transistor (MN
1
) in the floating condition.
That is, the voltage on the input pad
14
becomes “VDD-Vthn” when the input pad
14
is in the floating condition.
When the input pad
14
is in the floating condition and driven to “VDD-Vthn” by the PMOS transistor (MP
1
) (an operation condition known as the “pull-up mode”), there is a problem in that the input pad
14
is not driven to the full VDD level due to the Vthn drop of the NMOS transistor (MN
1
) at a transmission gate.
SUMMARY OF THE INVENTION
According to a feature of an embodiment of the present invention, there is provided a semiconductor integrated circuit device having a voltage interface circuit capable of driving an input pad to a full power supply voltage level in a pull-up mode.
According to another feature of an embodiment of the present invention, a semiconductor integrated circuit device is provided that includes a NMOS transistor having a first terminal connected to a pad, a second terminal connected to an internal circuit, and a gate connected to a power supply voltage used in the internal circuit.
The semiconductor integrated circuit device further includes a first PMOS transistor having a first terminal connected to the power supply voltage, a second terminal connected to the pad, and a gate connected to a first control signal.
The semiconductor integrated circuit device further includes a second PMOS transistor having a first terminal connected to the power supply voltage, a second terminal connected to the second terminal of the NMOS transistor, and a gate connected to a second control signal.
The semiconductor integrated circuit device further includes a voltage detection circuit for detecting whether a voltage on the pad is higher than the power supply voltage, and for generating a detection signal.
The semiconductor integrated circuit device further includes a control signal generating circuit for generating complimentary first and second control signals in response to the detection signal.
According to a device of an embodiment of the present invention, the input pad can be driven to the full power supply voltage level when the voltage on the input pad becomes lower than the power supply voltage in the floating condition.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.
REFERENCES:
patent: 5216292 (1993-06-01), Imazu et al.
patent: 5742183 (1998-04-01), Kuroda
patent: 6191617 (2001-02-01), Park
patent: 6275075 (2001-08-01), Min
patent: 6307399 (2001-10-01), Lien et al.
patent: 6445226 (2002-09-01), Taniguchi
Cox Cassandra
Lee & Sterba, P.C.
Samsung Electronics Co,. Ltd.
Wells Kenneth B.
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