Semiconductor integrated circuit device with test data...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C365S201000

Reexamination Certificate

active

07047461

ABSTRACT:
A semiconductor integrated circuit device includes test data output nodes arranged in a width of a plurality of bits and an internal data bus, greater in bit width than the test data output nodes, for transferring internal data. A predetermined number of bits of the internal data on the internal data bus are compared with bits of test expected value data equal in bit width to the test data output nodes for each bit. The predetermined number of bits of the internal data are selected in accordance with a test address signal. The bits selected is compared with the respective bits of the test expected valued data. Data indicating respective comparison results are output to the test data output nodes in parallel.

REFERENCES:
patent: 5040150 (1991-08-01), Naitoh et al.
patent: 5903576 (1999-05-01), Yoshiba
patent: 5991232 (1999-11-01), Matsumura et al.
patent: 6324666 (2001-11-01), Nakamoto
patent: 6418067 (2002-07-01), Watanabe et al.
patent: 6701470 (2004-03-01), Mullarkey et al.
patent: 6754865 (2004-06-01), Haraguchi
patent: 11-219600 (1999-08-01), None

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