Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-05-16
2006-05-16
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
07047461
ABSTRACT:
A semiconductor integrated circuit device includes test data output nodes arranged in a width of a plurality of bits and an internal data bus, greater in bit width than the test data output nodes, for transferring internal data. A predetermined number of bits of the internal data on the internal data bus are compared with bits of test expected value data equal in bit width to the test data output nodes for each bit. The predetermined number of bits of the internal data are selected in accordance with a test address signal. The bits selected is compared with the respective bits of the test expected valued data. Data indicating respective comparison results are output to the test data output nodes in parallel.
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Fujino Takeshi
Mangyo Atsuo
Yamazaki Akira
Britt Cynthia
De'cady Albert
McDermott Will & Emery LLP
Renesas Technology Corp.
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