Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2002-05-01
2004-09-07
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S194000, C365S205000
Reexamination Certificate
active
06788561
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit device, specifically to a technique effective for use in a device with a static type high-speed memory.
BACKGROUND OF THE INVENTION
Accompanied with progress in the micro fabrication of a semiconductor integrated circuit device, decrease in the spacing between adjoining wirings and thickening in the wiring layer have been creating a malfunction of coupling noises in the semiconductor integrated circuit device, resulting from a capacitance between the adjoining wirings in the same wiring layer. In order to reduce such coupling noises in the highly dense wirings, generally a shield wiring has been laid out to a signal wiring that receives the noises. In reverse to this, the Japanese Patent Application Laid-Open No. Hei 8(1996)125130 discloses a technique that disposes a wiring fixed to the ground potential of a circuit and a wiring fixed to the power supply potential to come close to a signal wiring regarded as a noise source less than virtually the thickness of an interlayer insulation film, and terminate the line of electric force from the signal wiring to the ground wiring or the power supply wiring to thereby reduce the influence to the other signal wirings.
SUMMARY OF THE INVENTION
As mentioned above, in either of the technique to reduce the coupling noises, which lays out the shield wiring to the signal wiring that receives the noises, or the technique disclosed in the publication, the common concept is to dispose a shield wiring to a signal transmission wiring, or in reverse to dispose a power supply wiring and a ground wiring that terminate the line of electric force to the signal wiring of the noise sources. That is, the conventional coupling noise reduction technique involves increase of the number of wirings for reducing the noises, which leads to an evil influence that substantially impairs the high-density wirings, and has incompatibility with the high-density wirings that cause the coupling noises.
The present invention has been made in view of the foregoing circumstances, and an object of the invention is to provide a semiconductor integrated circuit device that achieves reduction of the coupling noises without harming a high density of signal wirings. Another object of the invention is to provide a semiconductor integrated circuit device with memory circuits that realizes a high integration and low power consumption and high speed. The above and other objects and novel features of the invention will become apparent from the descriptions of this specification and accompanying drawings thereof.
The outline of the typical aspects of the invention disclosed here is as follows. That is, to a first signal line to which a signal with a comparably small amplitude against a power supply voltage is transmitted at a first timing, a latch type amplifier is connected which amplifies the small amplitude signal into a signal amplitude corresponding to the power supply voltage and the ground potential of the circuit, and a second signal line to which a voltage maintained at a constant is transmitted at the first timing is laid out on the same wiring layer as that of the first signal line adjacently to each other.
REFERENCES:
patent: 5650975 (1997-07-01), Hamade et al.
patent: 6091629 (2000-07-01), Osada et al.
patent: 6377483 (2002-04-01), Arimoto et al.
patent: 6424554 (2002-07-01), Kawasumi
patent: 8-125130 (1996-05-01), None
Funane Kiyotada
Ogura Kazutomo
Watanabe Noriyoshi
Dinh Son T.
Miles & Stockbridge P.C.
Renesas Technology Corp.
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