Patent
1980-05-22
1984-06-05
Clawson, Jr., Joseph E.
357 26, 357 45, 357 55, 357 235, H01L 2902
Patent
active
044531745
ABSTRACT:
Disclosed is a metal oxide semiconductor integrated circuit device having an array of electrically rewritable, insulated gate type non-volatile semiconductor memory cells formed on a semiconductor substrate, read/write mode setting circuit and address designating circuits arranged corresponding to the memory cell array, those circuits being fabricated on the substrate, and a field insulating layer formed on the substrate. A cut portion is formed in the field insulating layer to surround the memory cell array.
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Asano Masamichi
Iwahashi Hiroshi
Kawasaki Yuichi
Maekawa Shinichi
Mito Masazi
Clawson Jr. Joseph E.
Tokyo Shibaura Denki Kabushiki Kaisha
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