Semiconductor integrated circuit device with memory circuit

Details Semiconductor integrated circuit device with memory circuit Semiconductor integrated circuit device with memory circuit

2001-04-12

2002-10-15

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700

Reexamination Certificate

active

06466494

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices provided with memory circuits, and more particularly, to improvement of a redundant circuit of such memory circuit.
2. Description of the Background Art
FIG. 22
is a block diagram showing a configuration of a conventional semiconductor integrated circuit device. Referring to
FIG. 22
, the semiconductor integrated circuit device
1
is an application specific integrated circuit (ASIC) that includes random access memory (RAM) circuits (hereinafter, each simply referred to as a “memory circuit”) M
0
-M
3
and logic circuits L
0
-L
2
mounted irregularly on a single chip (semiconductor substrate) CH. Logic circuit L
0
uses memory circuit M
0
to process input data for application to logic circuit L
1
. Logic circuit L
1
uses memory circuits M
1
and M
2
to process data supplied from logic circuit L
0
for application to logic circuit L
2
. Logic circuit L
2
uses memory circuit M
3
to process data supplied from logic circuit L
1
for output.
Semiconductor integrated circuit device
1
further includes program circuits P
0
-P
3
provided corresponding to memory circuits M
0
-M
3
.
FIG. 23
is a block diagram showing only memory circuits M
0
-M
3
and program circuits P
0
-P
3
extracted from FIG.
22
.
Each of memory circuits M
0
-M
3
includes a redundant memory cell as well as a regular memory cell. When the regular memory cell is not defective, the regular memory cell is selected in response to an address signal A
0
-A
3
applied. Conversely, if the regular memory cell is defective, an address for specification of the memory cell is programmed in program circuit P
0
-P
3
. In such a case, when the applied address signal A
0
-A
3
matches the programmed address, the redundant memory cell is selected instead of the regular memory cell.
In the case of the semiconductor integrated circuit device
1
being ASIC as described above, it is often the case that memory circuits M
0
-M
3
are different in size from one another. In a large memory circuit, there is a high possibility that its memory cell suffers a defect. On the other hand, such possibility is low in a small memory circuit. Nevertheless, conventional semiconductor integrated circuit device
1
is generally provided with program circuits P
0
-P
3
corresponding to memory circuits M
0
-M
3
, of which some program circuits would never be utilized. Since program circuits P
0
-P
3
are configured by fuses fusable by laser, miniaturization of the program circuits is more difficult than that of the memory circuits and logic circuits which are formed of transistors. Accordingly, the presence of such unused program circuits leads to degradation in efficiency of chip area.
Japanese Patent Laying-Open No. 7-282596 discloses a technique to provide a single memory circuit having a memory cell array divided into a plurality of blocks, with a program circuit that can be shared by rows and columns on the block basis. This reference, however, does not describe any technique applicable to a semiconductor integrated circuit device having a plurality of memory circuits like an ASIC.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit device with reduced chip area being occupied by a program circuit.
The semiconductor integrated circuit device according to the present invention includes a plurality of memory circuits, a select circuit, and a shared program circuit. The plurality of memory circuits receive address signals different from each other. Each memory circuit includes a regular memory cell and a redundant memory cell. The select circuit selects at least one of the plurality of memory circuits. The shared program circuit is provided for the plurality of memory circuits. In the shared program circuit, it is possible to program an address of the regular memory cell that should be replaced by the redundant memory cell in the memory circuit selected by the select circuit.
Preferably, the select circuit includes a plurality of transmission circuits and an activation circuit. The plurality of transmission circuits respectively transmit a program signal representing the address programmed in the shared program circuit to the plurality of memory circuits. The activation circuit selectively activates the plurality of transmission circuits. Still preferably, the plurality of transmission circuits are provided corresponding to the plurality of memory circuits.
In this semiconductor integrated circuit device, the shared program circuit is provided for the plurality of memory circuits. Accordingly, chip area occupied by such shared program circuit is reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5293348 (1994-03-01), Abe
patent: 5576633 (1996-11-01), Roundtree et al.
patent: 5999463 (1999-12-01), Park et al.
patent: 07-282596 (1995-10-01), None
patent: 92/20068 (1992-11-01), None

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