Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-10-14
2003-06-24
Nguyen, Cuong Q (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06583463
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to a semiconductor integrated circuit device and a method of manufacturing the same and, more particularly, it relates to a technology that is effectively applicable to the manufacture of a semiconductor integrated circuit device in order to enhance the storage capacitance of DRAM (dynamic random access memory).
2. Description of the Prior Art
In a DRAM, the memory cells are disposed on the respective crossings of the word lines and the bit lines arranged in the form of matrix on the main surface of the semiconductor substrate, each memory cell comprising a MISFET (Metal Insulator Semiconductor Field Effect Transistor) to be used for selecting the memory cell and an information storage capacitor. The memory cell selecting MISFET is formed in an active region surrounded by a device isolation region and comprises as main components thereof a gate oxide film, a gate electrode integral with the corresponding word line and a pair of semiconductor regions constituting a source and a drain. The corresponding bit line is located above the memory cell selecting MISFET and electrically connected to either the source or the drain shared by the memory cell selecting MISFET and another memory cell selecting MISFET located adjacent to it. The information storage capacitor is also located above the memory cell selecting MISFET and electrically connected to the drain or the source not shared by the two MISFETs.
Japanese Patent Application Laid-Open No. 7-7084 discloses a DRAM having a so-called capacitor over bit line (COB) structure of arranging information storage capacitors above bit lines. In the disclosed DRAM, the lower electrodes (storage electrodes) of the information storage capacitors arranged above the bit lines are made to have a cylindrical profile to raise the surface area thereof in order to compensate the reduction in the stored electric charge (Cs) of the information storage capacitors given rise to by the extremely reduced size of the memory cells and the capacitor insulator and the upper electrode (plate electrode) of each memory cell is arranged above the information storage capacitor.
Japanese Patent Applications Laid-Open Nos. 64-42161 and 1-187847 disclose a technique of producing fine undulations on the surface of the lower electrodes of the information storage capacitors to raise the surface area thereof and secure the necessary storage capacitance by using poly-crystalline silicon for the lower electrodes and utilizing the phenomenon that the growth of granular poly-crystalline silicon depends on the surface condition of the under-layer in the initial stages of forming the poly-crystalline silicon by means of chemical vapor deposition (hereinafter referred to as CVD) or that the difference of the etching rate between boundary and bulk of the poly-crystalline silicon.
Finally, Japanese Patent Application Laid-Open No. 8-167702 discloses a technique of securing the necessary storage capacitance of an information storage capacitor comprising a first electrode (lower electrode) having a fin structure, a second electrode (upper electrode) and a dielectric material formed between the first and second electrodes by forming the first electrode from a material containing ruthenium oxide and the dielectric material from a material containing tantalum pentoxide so that the storage capacitance of the capacitor may be secured by the high dielectric constant of the material containing tantalum pentoxide.
SUMMARY OF THE INVENTION
However, the demand for a higher degree of integration gives rise to an ever-increasing demand for memory cells occupying a smaller area that cannot be met by the technique of raising the surface area of the lower electrode of each information storage capacitor by giving a cylindrical profile to it as proposed by Japanese Patent Application Laid-Open No. 7-7084 nor by forming fine undulations on the surface as proposed by Japanese Patent Applications Laid-Open Nos. 64-42161 and 1-187847. Thus, there is a demand for a technique of increasing the surface area of the lower electrode that cannot be met by simply providing it with a cylindrical profile because the height of the cylinder is limited by the mechanical strength required to the lower electrode and the stepped arrangement of the memory cell array region and the periphery circuit region due to the height of the lower electrodes nor by forming fine undulations on the surface of the lower electrode because they depend on the surface condition and the physical properties of the silicon of the device.
As for the technique of using a material having a high dielectric constant such as tantalum pentoxide for the capacitor insulator of the information storage capacitor disclosed by Japanese Patent Application Laid-Open No. 8-167702, the capacitor insulator is made of tantalum oxide film having a film thickness of 2.5 nm or more as expressed in terms of equivalent thickness of silicon oxide film. However, it is not possible for the technique to secure the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation. Thus, there still remains the problem of securing a sufficient effective surface area if lower electrodes having a fin structure are used.
Additionally, if the capacitor insulator is made of tantalum oxide film, it is difficult to use silicon (poly-crystalline silicon film) for the lower electrode because, if silicon is exposed to an oxygen containing atmosphere during the process of forming tantalum oxide, a silicon oxide film having a low dielectric constant is formed along the interface of the lower electrode and the tantalum oxide film to increase the effective film thickness of the capacitor insulator and, therefore, decrease the effective dielectric constant of the capacitor insulator to reduce the stored electric charge. In view of this problem, Japanese Patent Application Laid-Open No. 8-167702 proposes the use of ruthenium oxide for the lower electrode as a material that can prevent the generation of a low dielectric constant layer.
However, if the typical process of depositing ruthenium by sputtering and subsequently oxidizing the deposited ruthenium layer is used to produce ruthenium oxide, undulations appear on the surface of the ruthenium oxide film to damage the reliability of the information storage capacitor.
In view of the above identified problems of the prior art, it is therefore an object of the present invention to provide a technology that can effectively secure a required storage capacitance for the information storage capacitors of the memory cells of a 256 Mbits DRAM or a DRAM of a later generation.
Another object of the present invention is to provide a technology that makes it possible to use tantalum oxide for the capacitor insulator of information storage capacitor without lowering the effective dielectric constant of the capacitor insulator and raising the film thickness of the insulator if thermally treated in an oxygen containing atmosphere.
Still another object of the present invention is to provide a technology of planarizing the surface of the lower electrode of information storage capacitor to improve the reliability of the information storage capacitor.
Still another object of the present invention is to provide a technology that makes it possible to simplify the profile of the lower electrode and the process of producing it.
A further object of the present invention is to provide a technology of improving the insulation effect of the capacitor insulator of information storage capacitor and reduce the leak current in order to improve the performance and the reliability of the information storage capacitor.
A further object of the present invention is to optimize the material of the upper electrode of information storage capacitor and provide a highly reliable information storage capacitor.
A still further object of the present invention is to raise the stored electric charge of the information storage capacitors of the memory cells of
Iijima Sinpei
Kanai Misuzu
Kobayashi Nobuyoshi
Nakanishi Naruhiko
Ohji Yuzuru
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Nguyen Cuong Q
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