Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-08-23
2003-04-01
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700, C365S189050
Reexamination Certificate
active
06542419
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 U.S.C. §119 to Japanese Patent Application No. 2000-254151, filed on Aug. 24, 2000, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device including an electrically programmable fuse.
2. Related Background Art
A semiconductor integrated circuit on which a memory is mounted hitherto includes a redundancy circuit to relieve defective memory cells. The redundancy circuit comprises a spare cell array configured to replace a defective cell and disposed separately from a normal cell array and a fail address storage circuit configured to store an address of the defective cell and detect a coincidence of an address inputted from the outside and the fail address to output a replacing signal.
A fuse is usually used in the fail address storage circuit. A laser blown fuse is typical of this kind of fuse. The fail address is stored by blowing a fuse corresponding to the fail address detected by a die sort test in a wafer stage.
Since the laser blown fuse is blown by the irradiation of a laser beam from the outside, it can not cope with defects detected after an integrated circuit chip is packaged. The use of an electrically programmable fuse is required to enable programming even after the integrated circuit chip is packaged. A method of using a capacitor-type fuse, which uses a thin insulating film and becomes conductive by destroying the insulating film by the application of high voltage, as such a fuse is already disclosed (See U.S. Pat. No. 5,110,754, for example).
When the aforesaid capacitor-type fuse to be electrically programmed is used, however, a test for analyzing the fail address after the packaging of the integrated circuit chip is necessary, which causes an increase in test cost. In the case of a DRAM mounted on a logic integrated circuit (embedded DRAM), there are very few pins for testing a DRAM section, and thus it is difficult to test the DRAM section by inputting an address and data from the outside.
To eliminate such disadvantages, a method of mounting a BIST (Built In Self-test) circuit to test a memory cell array internally together with a fuse to be programmed electrically on a chip is disclosed (See U.S. Pat. No. 5,313,424, for example). This BIST circuit automatically tests a cell array by a trigger signal from the outside to detect fail addresses. The detected fail addresses are transferred to a fuse circuit and electrical programming is performed.
In BIST circuit methods hitherto disclosed, however, a dedicated register to hold fail addresses detected automatically is used, and besides a complicated control circuit is required to control the fuse circuit. For this reason, there is a disadvantage that the area of the integrated circuit chip increases.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a semiconductor integrated circuit device, comprising:
a fuse to be electrically programmed;
a data latch circuit configured to hold fuse data programmed into the fuse after the fuse is programmed;
a data preset circuit configured to preset data to be programmed into the fuse in the data latch circuit before the fuse is programmed; and
a programming selecting circuit configured to monitor a state of data in the data latch circuit and select whether to perform or not to perform a programming operation for the fuse.
According to another aspect of the present invention, a semiconductor integrated circuit device, comprising:
a memory cell array having a normal cell array and a spare cell array for replacing a defect cell in the normal cell array;
a decode circuit configured to select a memory cell from the memory cell array; and
a fail address storage circuit configured to store a fail address and output a replacing signal when an inputted address coincides with the fail address to switch-control the decode circuit so that the spare cell array is selected, the fail address storage circuit including;
a plurality of fuses to be electrically programmed;
data latch circuits provided in the respective fuses to hold fuse data programmed into the fuses after the fuses are programmed;
data preset circuits configured to preset fail address data to be programmed in the respective data latch circuits before the fuses are programmed; and
programming selecting circuits configured to monitor states of data in the respective data latch circuits and select whether to perform or not to perform a programming operation for each of the fuses; and
a programming control circuit configured to divide the plurality of fuses into a plurality of groups and perform an operation of programming fuses all at once in the respective groups in turn.
According to a further aspect of the present invention, a semiconductor integrated circuit device, comprising:
a plurality of fuses to be electrically programmed;
data latch circuits provided in the respective fuses to latch data to be programmed in the fuses;
programming selecting circuits configured to monitor states of data in the respective data latch circuits and select whether to perform or not to perform a programming operation for each of the fuses;
a programming control circuit configured to divide the plurality of fuses into a plurality of groups and perform an operation of programming fuses all at once in the respective groups in turn; and
read circuits configured to perform a read operation of fuse data programmed in each fuse after a programming operation for a plurality of fuses in a predetermined group by the programming control circuit,
wherein the programming control circuit comprises:
a completion judging circuit configured to judge in each group whether programming for all fuses to be programmed in the group is completed or not based on the read operation by the read circuit; and
a selecting signal output circuit configured to output a selecting signal for activating the programming selecting circuits in each group in sequence in response to a judging signal obtained from the completion judging circuit.
REFERENCES:
patent: 5110754 (1992-05-01), Lowrey et al.
patent: 5313424 (1994-05-01), Adams et al.
patent: 5495446 (1996-02-01), Teel et al.
patent: 5668818 (1997-09-01), Bennett et al.
patent: 5956282 (1999-09-01), Casper
patent: 6166981 (2000-12-01), Kirihata et al.
patent: 6178125 (2001-01-01), Niiro
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