Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-28
2007-08-28
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10786552
ABSTRACT:
An area for layout of a plurality of I/O cells (called an “I/O area”) is provided in the peripheral portion of a chip and signal wirings for transferring test signals to the I/O cells are provided in the layout direction of the I/O cells. At least one empty cell provided in the I/O area at a position where I/O cells are not provided has a repeater circuit which constitutes a transfer path for the test signal. The repeater circuit receives the test signal and outputs the test signal. This structure provides a suitable semiconductor integrated circuit device adaptable for an ASIC or the like, which can adjust the delay of a test signal to be transferred along the chip's peripheral portion by suppressing an increase in the delay and degradation in waveform depression.
REFERENCES:
patent: 5509019 (1996-04-01), Yamamura
patent: 5983376 (1999-11-01), Narayanan et al.
patent: 6145116 (2000-11-01), Tawada
patent: 6564362 (2003-05-01), Osaki et al.
patent: 6983436 (2006-01-01), Amekawa
patent: 7000163 (2006-02-01), Dirks et al.
patent: 2002/0004929 (2002-01-01), Osaki et al.
patent: 2004/0006754 (2004-01-01), Sonohara
patent: 6-160480 (1994-06-01), None
patent: 7-176579 (1995-07-01), None
patent: 10144796 (1998-05-01), None
patent: 2000022081 (2000-01-01), None
patent: 2002-26129 (2002-01-01), None
patent: 2004047516 (2004-02-01), None
patent: 2004172373 (2004-06-01), None
Jones, T.R.: “JTAG Clock & Control Signal Distribution Scheme” Motorola Technical Developments, Motorola Inc. Schaumburg, Illinois, US, vol. 18, Mar. 1, 1993, pp. 44-49.
Kuge Hiroyoshi
Ohara Yoshihiro
Garbowski Leigh M.
NEC Electronics Corporation
Young & Thompson
LandOfFree
Semiconductor integrated circuit device with boundary scan... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device with boundary scan..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device with boundary scan... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3877336