Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-05-23
2003-09-23
Tran, M (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
06625072
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a semiconductor integrated circuit device, and more specifically, concerns a semiconductor integrated circuit that is provided with a testing circuit for carrying out a test on a semiconductor memory device.
2. Description of the Background Art
Most of semiconductor devices have a redundant memory cell, and when there is a defective memory cell in one portion of the memory cell, it replaces the defective portion with the redundant memory cell so as to repair the defective chip.
FIG. 28
is a schematic block diagram that shows the structure of a redundant circuit that is installed with respect to a memory array section
8010
of such a semiconductor memory device.
One memory cell in memory array
8010
is selected by a row address signal RA
0
-
13
and a column address signal CA
0
-
8
that are externally inputted. In this one memory cell thus selected, during a writing operation, data supplied to a data input/output terminal DQ (not shown) is written. Moreover, during a reading operation, read data is outputted from memory array
8010
to this data input/output terminal DQ.
A row decoder
8020
selects a memory cell corresponding to one row to be read or written in accordance with the inputted row address. Moreover, a column decoder
8030
carries out a selection of one column based upon a column address inputted so that, among memory cells corresponding to one row selected by the row address, one memory cell is further selected.
The above-mentioned detection of a defective memory cell and an analysis for replacing the defective memory cell with a redundant memory cell array are generally carried out by a memory tester that is placed outside of the semiconductor memory device.
In recent years, however, a semiconductor memory device or a semiconductor device having a semiconductor memory device, which is provided with a so-called built-in type testing device that has a build-in signal generator within a semiconductor memory device to be tested or within a semiconductor device on which a semiconductor memory device is installed so that the testing process is carried out without using the memory tester, has been manufactured.
However, in such a semiconductor memory device or a semiconductor device provided with such a build-in testing device, although it is possible to carry out the test for determining as to whether or not any detective memory exists, it is difficult to carry out a test for achieving a redundant analysis on the device itself. This is because, as described earlier, a fail memory for storing the addresses of defective memory cells requires a memory of which capacity is as large as the semiconductor memory device or the built-in the semiconductor memory device in the semiconductor device to be measured; therefore, in fact, it is difficult to install such a fail memory in the semiconductor memory device or the semiconductor device, and consequently, it is not possible to carry out the redundant analysis.
[An Arrangement in Which One Bit Data is Read Out Per One Memory Cell]
In order to solve the above-mentioned problems, Japanese Patent Laying-Open No. 2001-6387 discloses the following arrangement.
FIG. 29
is a schematic block diagram that shows the entire structure of a dynamic-type semiconductor memory device (hereinafter, referred to as DRAM)
9000
disclosed by Japanese Patent Laying-Open No. 2001-6387, where one-bit data is read out per sub-memory alley.
Referring to
FIG. 29
, DRAM
9000
is provided with a control signal input terminal group
11
for receiving a control signal such as a row address strobe signal/RAS, an address input terminal group
13
for receiving address signals A
0
to Ai (i: natural number) and a data input/output terminal group
15
for carrying out data input/output operations.
DRAM
9000
is further provided with a control circuit
26
for generating an internal control signal for controlling the entire operation of DRAM
9000
in accordance with a control signal; an internal control signal bus
72
for transmitting the internal control signal; an address buffer
30
for generating an internal address signal upon receipt of an external address signal from address input terminal group
13
; and a memory cell array
100
having a plurality of memory cells MC arranged in a matrix manner.
Here, it is assumed that one-bit data is read out per one memory cell array
100
.
The internal address signals refer to, for example, mutually complementary internal row address signals RA
0
-
13
and/RA
0
-
13
generated from external row address signal RA
0
-
13
and mutually complementary internal column address signals CA
0
-
8
and /CA
0
-
8
generated from external row address signal CA
0
-
8
.
In the same manner as memory cell array section
8010
shown in
FIG. 28
, a memory cell array
100
shown in
FIG. 29
includes a normal memory cell array
100
R, a spare row SR and a spare column SC.
In memory cell array
100
also, with respect to spare rows SR, two spare rows SR
1
and SR
2
are installed, and with respect to spare columns SC, two spare columns SC
1
and SC
2
are installed.
DRAM
9000
is further provided with a built-in self test circuit (hereinafter, referred to as BIST circuit)
7000
for detecting a defective memory cell in DRAM
9000
and for carrying out a testing operation for replacing it with a spare row SR or a spare column SC.
During a normal operation, BIST circuit
7000
, which is controlled by a control circuit
26
, outputs an internal row address signal and an internal column address signal from address buffer
30
, as they are, to a row decoder, a spare row decoder
42
, a column decoder
50
and a spare column decoder
52
respectively. Moreover, during the normal operation, BIST circuit
7000
receives written data, which has been supplied from data input/output terminal group
15
, subjected to a buffer process by an input/output buffer
85
, and outputted from a writing driver
80
, and outputs the data as it is to a row selection gate
200
.
In contrast, during a testing operation, BIST circuit
7000
gives not an internal address signal from address buffer
30
, but an internal address signal generated inside BIST circuit
7000
, to row decoder
40
, spare row decoder
42
, column decoder
50
and spare column decoder
52
respectively. Moreover, not data supplied from writing driver
80
, but testing-use writing data TD, generated inside BIST circuit
7000
, is given to a column selection gate
200
so that the test data is written in memory cell array
100
.
Upon completion of the writing operation in such a testing operation, BIST circuit
7000
again generates an internal address signal so as to read out written data successively. In accordance with the results of comparisons between the read data and expected value data ED, BIST circuit
7000
successively detects the position of a defective memory cell in a normal memory cell array
100
R, and determines what combination between spare row SR and spare column SC is used for replacing a plurality of defective row addresses and defective column addresses corresponding to such a plurality of defective memory cells.
In accordance with the determination as described above, an external tester gives instructions to a repair device so that, for example, the repair device trims fuse elements in spare row decoder
42
and spare column decoder
52
.
FIG. 30
is a schematic block diagram that explains the arrangement of an address replacement determining device
8000
contained in BIST circuit
7000
.
First, prior to explaining the structure of address replacement determining device
8000
, an explanation will be briefly given of a processing sequence for replacing the defective addresses in memory cell array
100
in
FIG. 29
with spare row SR and spare column SC.
In the following description, it is assumed that a defective memory cell distribution that is the same as the defective memory cells in memory cell array section
8010
shown in
FIG. 28
occurs
Kawagoe Tomoya
Ohtani Jun
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Tran M
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