Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-07-30
2004-02-03
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185010, C365S185100, C365S185170, C365S185260, C365S185060
Reexamination Certificate
active
06687156
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor integrated circuit device, and a production and operation method thereof. More particularly, this invention relates to a technology that will accomplish high integration density, high reliability and low operating voltage of an electrically programmable/erasable non-volatile semiconductor memory device.
Among electrically programmable/erasable nonvolatile semiconductor memory devices, a so-called “flash memory” is known as a memory device capable of collectively erasing data. The flash memory has excellent portability and impact resistance, and can electrically and collectively erase the data. Therefore, the demand for the flash memory has been increasing rapidly in recent years as a file (memory device) for compact personal digital assistants such as portable personal computers, digital still cameras, and so forth. To expand the market, reduction of a bit cost by the reduction of a memory cell area is of utmost importance, and various memory cell systems for accomplishing this object have been proposed as described in, for example, “Ohyo Butsuri (or Applied Physics)”, Vol. 65, No. 11, p 1114-1124 published by the Japan Society of Applied Physics, Nov. 10, 1996.
On the other hand, JP-B-2,694,618 (Reference 1 corresponding to U.S. Ser. No. 204,175 filed on Jun. 8, 1988) describes a virtual ground type memory cell that uses a three-layered polysilicon gate. In other words, this memory cell comprises a semiconductor region formed in a well of a semiconductor substrate and three gates. The three gates are a floating gate formed on the well, a control gate formed on the floating gate and an erase gate formed between the control gate and the floating gate adjacent to each other. Each of the three gates comprises polysilicon and is isolated by an insulator film. The floating gate and the well, too, are isolated from each other by an insulator film. The control gate is connected in a row direction and constitutes a word line. A source/drain diffusion layer is formed in a column direction and shares the diffusion layer with an adjacent memory cell in a virtual ground type. The pitch in the column direction is thus reduced. The erase gate is in parallel with a channel and is disposed between the word lines (control gates) also in parallel with the word lines.
To execute program the memory cell in this Reference 1, mutually independent positive voltages are applied to the word line and to the drain, respectively, while the well, the source and the erase gate are kept at 0 V. In consequence, hot electrons develop in the channel portion in the proximity of the drain, the electrons are injected into the floating gate and the threshold voltage of the memory cell rises. To erase the memory content, a positive voltage is applied to the erase gate while the word line, the source/drain and the well are kept at 0 V. Consequently, the electrons are ejected from the floating gate to the erase gate and the threshold voltage drops.
JP-A-9-321157 (Reference 2, laid-open on Dec. 12, 1997), for example, discloses a split gate type memory cell. A large overlap area is secured between a diffusion layer and a floating gate so that the potential of the diffusion layer increases the potential of the floating gate. A low voltage is applied to a word line so as to improve the generation of hot electrons and the injection effect when data is written.
Furthermore, “International Electron Devices Meeting Technical Digest”, 1989, pp. 603-606 (Reference 3) discusses a method that controls a floating gate potential by a word line and controls a split channel by a third gate that is different from both floating gate and control gate.
SUMMARY OF THE INVENTION
However, the inventors of the present invention have found that several problems develop when a higher integration density is sought in the memory cells described above. Incidentally, the problems that follow are noticed by the present inventors and are not particularly known in the art.
First, in order to miniaturize a memory cell, scale-down in a direction vertical to an extending direction of a data line (that is, the direction of the arrangement of the data line) as well as scale-down in a direction vertical to an extending direction of a word line (that is, the direction of the arrangement of the word line) must be achieved. Reduction of the word line width and the word line gap is effective for achieving the reduction in the word line arrangement direction. However, when the word line width is decreased, the resistance value of the word line increases with the result that the rise of the word line voltage is retarded when the data is written or read out. This invites in turn the problem of the drop of the operation speed. To solve this problem, a stacked film of a polysilicon film and its metal silicide film (that is, a so-called “polycide film”) may be used in place of the polysilicon single film as a word line material. The polycide film provides a film having a lower resistance value than the polysilicon film having the same film thickness and can restrict the rise of the word line resistance. When miniaturization further proceeds in future and the word line with is required to be smaller than as it now is, a stacked film of the polysilicon film and a metal film (that is, a so-called “polymetal film”) may be used. The polymetal film can further lower the resistance value than the polycide film having the same film thickness and can cope with the further reduction of the word line width.
However, the following problems develop when the polycide film or the polymetal film is used as the word line material. In the memory cell described in the reference cited above, the erase gate and the word line are so arranged as to extend in the direction vertical to the data line direction. In order to reduce the gap between the word lines to twice the minimum feature size, it is necessary to pattern continuously the word line and the floating gate, then to form the insulator film between the floating gates so formed, and to form thereafter the erase gate. However, metals contained in the polycide or in the polymetal dissolve during a cleaning step as a pre-step for forming the insulator film between the floating gate and the erase gate. The dissolving metals again adhere to the sidewalls of the floating gate and are entrapped into the insulation film during the subsequent formation step of the insulator film. As a result, the defect density of the insulatot film increases and reliability is spoiled.
Second, the memory cell described in the above-mentioned reference employs a memory cell structure called a “split channel type” in which the floating gate does not exist at a part of the channel portion. Control of the split channel in this memory cell is achieved as the potential of the control gate (word line) existing on that split channel is controlled. Therefore, the word line has also the function of the split gate.
Incidentally, to write the data into the memory cell, it is necessary to increase the occurrence quantity of hot electrons and injection efficiency. To attain this object, it is effective to increase the potential of the floating gate so as to increase the electric field in the vertical direction of the channel portion, and to lower the potential of the split gate to increase the electric field in the channel horizontal direction.
In the memory cell described in the Reference 1, however, the voltage of the split gate is controlled through the word line voltage. Therefore, the voltages of the floating gate and the split gate cannot be controlled independently. In other words, there is no way but to control the voltages of both floating gate and split gate through the word line voltage. In consequence, the generation of the hot electrons and injection efficiency cannot be improved simultaneously. When the data is programmed, therefore, an extremely large current with respect to the injection current flows, and the data cannot be programmed simultaneously into a plurality of memory cells
Kimura Katsutaka
Kobayashi Naoki
Kobayashi Takashi
Kume Hitoshi
Kurata Hideaki
Hitachi , Ltd.
Nguyen Viet Q.
LandOfFree
Semiconductor integrated circuit device, production and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device, production and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device, production and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3317532