Semiconductor integrated circuit device, process for fabricating

Details Semiconductor integrated circuit device, process for fabricating Semiconductor integrated circuit device, process for fabricating

1997-10-03

2000-10-03

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438622, 438631, 438668, 438688, 438780, 438787, 438791, H01L 214763, H01L 21469

Patent

active

061272558

ABSTRACT:
Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.

REFERENCES:
patent: 4468411 (1984-08-01), Sloan et al.
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4636404 (1987-01-01), Raffel et al.
patent: 4767724 (1988-08-01), Kim et al.
patent: 4782380 (1988-11-01), Shankar et al.
patent: 4824803 (1989-04-01), Us et al.
patent: 4871688 (1989-10-01), Lowrey
patent: 4872947 (1989-10-01), Wang et al.
patent: 4882289 (1989-11-01), Moriuchi et al.
patent: 4892753 (1990-01-01), Wang et al.
patent: 4920072 (1990-04-01), Keller et al.
patent: 4933303 (1990-06-01), Mo
patent: 4937645 (1990-06-01), Ootsuka et al.
patent: 4950624 (1990-08-01), Inuzima et al.
patent: 4960488 (1990-10-01), Law et al.
patent: 4962052 (1990-10-01), Asayama et al.
patent: 4962060 (1990-10-01), Sliwa et al.
patent: 4962063 (1990-10-01), Maydan et al.
patent: 4977102 (1990-12-01), Ema
patent: 4986878 (1991-01-01), Malazgirt et al.
patent: 4994893 (1991-02-01), Ozaki et al.
patent: 5000113 (1991-03-01), Wang et al.
patent: 5010024 (1991-04-01), Allen et al.
patent: 5013689 (1991-05-01), Yamamoto et al.
patent: 5057897 (1991-10-01), Nariani et al.
patent: 5128744 (1992-07-01), Asamo et al.
patent: 5158644 (1992-10-01), Cheung et al.
patent: 5192715 (1993-03-01), Sliwa, Jr. et al.
patent: 5314845 (1994-05-01), Lee et al.
patent: 5354387 (1994-10-01), Lee et al.
patent: 5354715 (1994-10-01), Wang et al.
patent: 5362526 (1994-11-01), Wang et al.
patent: 5514624 (1996-05-01), Morozumi
Thomel, et al., "Al, O.mu.m CMOS Two Level Metal Technology Incorporating Plasma Enhanced TEOS", 1987 Proceed of Fourth Int. IEEE VLSI Multilevel Interconnecting Conference, 1987 Abstract.
S. Wolf, Silicon Processing Fourth VLSI Era, vol. 2, Lattice Press, pp. 198-199, 211-212, 1990.

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