Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Reexamination Certificate
2011-04-12
2011-04-12
Lauture, Joseph (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
C341S101000
Reexamination Certificate
active
07924185
ABSTRACT:
A shift register SR configured to successively take in and hold input serial data on the basis of a first clock signal, a pattern detection section configured to detect a predetermined pattern contained in the serial data taken in the shift resister and a second clock generation section configured to determine timing of output of the serial data held in the shift register on the basis of a result of this detection are provided to detect the desired pattern contained in the serial data in the course of transferring the serial data for conversion from the serial data to parallel data to the shift resister, and to determine timing of conversion to the parallel data on the basis of a result of this detection, thus reducing the latency and achieving an improvement in communication speed and a reduction in circuit area.
REFERENCES:
patent: 5287389 (1994-02-01), Ichibangase et al.
patent: 6265996 (2001-07-01), Duffy
patent: 6459393 (2002-10-01), Nordman
patent: 6999543 (2006-02-01), Trinh et al.
patent: 7463171 (2008-12-01), Baba
Kabushiki Kaisha Toshiba
Lauture Joseph
Turocy & Watson LLP
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