Semiconductor integrated circuit device operating with low...

Details Semiconductor integrated circuit device operating with low... Semiconductor integrated circuit device operating with low...

2001-02-06

2003-10-21

Eckert, George (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S500000, C326S031000, C326S033000, C326S083000, C326S121000, C327S391000, C327S546000

Reexamination Certificate

active

06635934

ABSTRACT:

BACKGROUND OF THE PRESENT INVENTION
1. Field of the Present Invention
The present invention relates to a semiconductor device including insulated gate field effect transistors, referred to as “MIS transistors” hereinafter, as it components, and particularly to a configuration for reducing power consumption in a semiconductor device having miniaturized CMOS transistors (P- and N-channel MIS transistors). More particularly, the present invention relates to a structure for suppressing a gate tunnel current of a miniaturized MIS transistor.
2. Description of the Background Art
In a CMOS semiconductor device, as the size of MIS transistors is reduced, an operation power supply voltage is lowered for ensuring reliability of the transistors and reducing power consumption. For reducing the sizes of MIS transistors in accordance with lowering of the operation power supply voltage, values of various transistor parameters are reduced according to a certain scaling rule. According to the scaling rule, it is necessary to reduce a thickness Tox of a gate insulating film of the MIS transistor, and it is also necessary to reduce an absolute value Vth of a threshold voltage. However, it is difficult to reduce the absolute value of the threshold voltage according to the scaling rule. The threshold voltage is defined as a gate-source voltage, which causes a predetermined drain current under application of a predetermined drain voltage. If absolute value Vth of the threshold voltage is small, a weak inversion layer is formed in a channel region even with a gate-source voltage Vgs being 0 V, and a sub-threshold leak current, referred to as an “off-leak current” hereinafter, flows through this inversion layer.
Therefore, such a problem occurs that the off-leak current increases to increase the standby current in a standby cycle during which MIS transistors are off. Particularly, in a semiconductor device for use in a battery-powered equipment such as a portable equipment, it is greatly required to reduce the off-leak current in view of a lifetime of the battery.
For reducing the off-leak current, absolute value Vth of the threshold voltage can simply be increased. In this case, however, reduction of the operation power supply voltage cannot achieve an intended effect, and fast operation cannot be ensured. Thus, an MT-CMOS (Multi-Threshold CMOS) structure has been proposed for reducing the off-leak current in the standby cycle and for ensuring fast operation.
FIG. 104
shows, by way of example, a structure of an MT-CMOS circuit in the prior art. In the structure shown in
FIG. 104
, five inverter circuits IV
0
-IV
4
are cascaded. For these inverter circuits IV
0
-IV
4
, there are arranged a main power supply line MVL coupled to a power supply node, a sub-power supply line SVL coupled to main power supply line MVL via a switching transistor SWP, a main ground line MGL coupled to a ground node, and a sub-ground line SGL coupled to main ground line MGL via a switching transistor SWN.
Inverter circuits IV
0
-IV
4
each have a structure of a CMOS inverter, and include P-channel MIS transistors P
0
-P
4
and N-channel MIS transistors N
0
-N
4
, respectively. This MT-CMOS circuit has a standby cycle in a standby state and an active cycle in which an input signal changes actually. In the standby cycle, input signal IN is fixed to L-level, and switching transistors SWP and SWN are kept in the off state in response to control signals /&phgr; and &phgr;, respectively. Each of switching transistors SWP and SWN has a threshold voltage relatively large (medium) in absolute value, M-Th. Each of MIS transistors P
0
-P
4
and N
0
-N
4
of inverter circuits IV
0
-IV
4
has a threshold voltage of a small absolute value, L-Th.
Depending on a logical level of an input signal IN in the standby cycle, a source of each MIS transistor, which is on in the standby cycle, is connected to main power supply line MVL or main ground line MGL. More specifically, sources of MIS transistors P
0
, P
2
and P
4
are connected to main power supply line MVL, and sources of MIS transistors N
1
and N
3
are connected to main ground line MGL. A source of each MIS transistor, which is off in the standby cycle, is connected to sub-power supply line SVL or sub-ground line SGL. More specifically, sources of MIS transistors P
1
and P
3
are connected to sub-power supply line SVL, and sources of MIS transistors N
0
, N
2
and N
4
are connected to sub-ground line SGL. Now, an operation of the MT-CMOS circuit shown in
FIG. 104
will now be described with reference to a signal waveform diagram of FIG.
105
.
During the standby cycle, input signal IN is at L-level, and control signals &phgr; and /&phgr; are at L- and H-levels, respectively. In this state, switching transistors SWP and SWN are off. Switching transistor SWP is an M-Vth transistor, and the off-leak current thereof in the standby state cycle is small.
In inverter circuits IV
0
-IV
4
, MIS transistors P
0
, P
2
and P
4
are on, and therefore do not cause a sub-threshold leak (off-leak) current. Meanwhile, MIS transistors P
1
and P
3
are off, and cause an off-leak current from sub-power supply line SVL. The off-leak currents flowing through MIS transistors P
1
and P
3
flow to main ground line MGL through MIS transistors N
1
and N
3
in the on state, respectively. However, the off-leak current flowing through MIS transistors P
1
and P
3
depends in magnitude on the off-leak current flowing through switching transistor SWP. Therefore, the voltage level of sub-power supply line SVL reaches an equilibrium state where the off-leak current flowing through switching transistor SWP is balanced with the sum of off-leak currents flowing through MIS transistors P
1
and P
3
. Due to the current flow, the voltage level of sub-power supply line SVL is lower than power supply voltage VCC, and MIS transistors P
1
and P
3
enters such a state that the gate to source thereof is reverse-biased, and therefore enters a deeper off state. Accordingly, MIS transistors P
1
and P
3
can have the off-leak currents sufficiently reduced.
Likewise, off-leak currents flow through MIS transistors N
0
, N
2
and N
4
. These off-leak currents flowing through MIS transistors N
0
, N
2
and N
4
depend in magnitude on the off-leak current flowing through switching transistor SWN. Switching transistor SWN is an M-Vth transistor, and has a sufficiently small off-leak current so that the off-leak currents of MIS transistors N
0
, N
2
and N
4
can be sufficiently suppressed.
In the above case, the voltage level of sub-ground line SGL reaches an equilibrium state where the sum of off-leak currents flowing through MIS transistors N
0
, N
2
and N
4
are balanced with the off-leak current flowing through switching transistor SWN, and therefore is higher than ground voltage GND. In this case, each of MIS transistors N
0
, N
2
and N
4
enters such a state that the gate to source thereof is reverse-biased, and therefore enters a deeper off state. Accordingly, MIS transistors N
0
, N
2
and N
4
can have the off-leak current sufficiently suppressed.
In the active cycle for actually performing an operation, control signals &phgr; and /&phgr; are set to H- and L-levels, respectively, and switching transistors SWP and SWN are turned off. Responsively, sub-power supply line SVL is connected to main power supply line MVL, and sub-ground line SGL is connected to main ground line MGL. Inverter circuits IV
0
-IV
4
include L-Vth transistors as components, and therefore, rapidly change their output signals in accordance with input signal IN.
As shown in
FIG. 104
, the power supply line differs in impedance value depending on the standby cycle and the active cycle. Thereby, even with the L-Vth transistors employed as its components, the off-leak current can be sufficiently suppressed in the standby cycle, while ensuring fast operation performance in the active cycle. Accordingly, a CMOS circuit capable of fast operation with low power consumption can be implemented.
Various parameters such as sizes of the MIS transistors are r

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