Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-03-22
2001-10-30
Fears, Terrell W. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
06310807
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, particularly to the structure of a semiconductor integrated circuit device mounted with a tester circuit to test a semiconductor memory device.
2. Description of the Background Art
Most semiconductor memory devices include spare memory cells to allow a defective memory cell, if present, to be replaced with the spare memory cell to repair the defective chip.
FIG. 32
is a schematic block diagram showing a structure of a redundant circuit provided for a memory array unit
8010
of such a semiconductor memory device.
One memory cell in memory array unit
8010
is selected by externally applied row address signals RA
0
-
13
and column address signals CA
0
-
8
. In a write operation, the data applied to a data input/output terminal DQ (not shown) is written into the selected one memory cell. In a readout operation, the data read out from memory array unit
8010
is provided to data input/output terminal DQ.
A row decoder
8020
responds to an input row address to select memory cells of one row for a read or write operation. A column decoder
8030
selects one column according to an input column address, and further selects one memory cell out of the one row of memory cells selected according to the row address.
Detection of a defective memory cell and analysis to replace that defective memory cell with a redundant memory cell array are generally carried out by an external memory tester of semiconductor memory device
8000
.
In these few years, a semiconductor memory device
8000
to be tested, or a semiconductor memory device including the so-called built-in test device that has a signal generator provided in a semiconductor device with a semiconductor memory device to carry out testing without a memory tester, or a semiconductor device incorporating a semiconductor memory device with such a built-in test device are produced.
In such a semiconductor memory device or semiconductor device incorporating such a built-in test device, it is difficult to carry out testing that realizes a redundancy analysis function itself even if the testing of whether there is a defective memory cell or not in the memory cell can be carried out. The failure memory to store the address of the defective memory cell requires a capacity equal to that of the semiconductor memory device to be tested or the semiconductor memory device incorporated in the semiconductor device. In practice, it is difficult to incorporate a failure memory of such a capacity in a semiconductor memory device or a semiconductor device. Therefore, redundancy analysis could not be carried out.
A trend is towards increased data bit width for the data input/output of a semiconductor memory device from the standpoint of speeding up the system. Accordingly, a plurality of memory cells are often selected simultaneously in the memory array. Therefore, the aforementioned redundancy analysis becomes more complicated.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device or a semiconductor integrated circuit device incorporating a semiconductor memory device including a built-in tester circuit that can detect, when a plurality of memory cells are selected simultaneously for every sub memory cell array, a defective memory cell, and replace the defective memory cell with a redundant memory cell.
According to an aspect of the present invention, a semiconductor integrated circuit device includes a memory cell array, a memory cell select circuit, a data transmission circuit, and a tester circuit.
The memory cell array has a plurality of memory cells arranged in a matrix. Each memory cell retains data. The memory cell array includes a normal memory cell array with a plurality of normal memory cells, a spare memory cell row including a plurality of spare memory cells, and a spare memory cell column including a plurality of spare memory cells. The memory cell select circuit selects at one time the plurality of memory cells belonging to the same one row in the memory cell array according to an address signal. The data transmission circuit transmits the stored data with respect to the selected plurality of memory cells. The tester circuit detects a defective memory cell in the memory cells and determines which of the spare memory cells is to be used for replacement. The tester circuit includes a comparison circuit, an address storage circuit, and a control circuit. The comparison circuit compares the data stored in the selected memory cell with expected value data in a test readout operation. The address storage circuit stores a defective address corresponding to the defective memory cell according to the comparison result of the comparison circuit. The control circuit controls the test operation. The control circuit determines that repair is to be carried out with the spare memory cell row when detection is made of a plurality of defective memory cells in the plurality of memory cells selected at one time.
Therefore, an advantage of the present invention is that, when a plurality of memory cells are selected simultaneously in a memory cell array, defective memory cell detection and redundancy analysis can be carried out with a relatively low circuit complexity, and that a tester circuit with the redundancy analysis function can be incorporated in the semiconductor integrated circuit device per se.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5487041 (1996-01-01), Wada
Co-pending U.S. patent application Ser. No. 09/459,710, filed Dec. 13, 1999.
Co-pending U.S. patent application Ser. No. 09/793,612, filed Feb. 27, 2001.
Hidaka Hideto
Ooishi Tsukasa
Fears Terrell W.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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