Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1994-06-02
1996-11-05
Chin, Wellington
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375375, 327158, 327156, 327161, 327162, H03D 324
Patent
active
055725570
ABSTRACT:
A semiconductor integrated circuit device including input and output registers, a data-processing circuit block disposed between the registers, a first PLL circuit for supplying a first output clock signal to the input register in response to an input clock signal, and a second PLL circuit for supplying a second output clock signal to the output register in response to the input clock signal. The input register transfers a data signal stored therein to the output register in response to the first output clock signal. The output register stores the data signal and transfers it to another device in response to the second output clock signal. The first and second PLL circuits supply the first and second output clock signals to the input and output registers with keeping the phase differences constant, respectively. The data signal stored in the input register can be correctly transferred to the output register, and the data signal stored in the output register can be correctly transferred to an input register of another semiconductor integrated circuit device even if the clock skew arises.
REFERENCES:
patent: 4456890 (1984-06-01), Carickhoff
patent: 4611230 (1986-09-01), Nienaber
patent: 4888564 (1989-12-01), Ishigaki
patent: 4972442 (1990-11-01), Steierman
patent: 5065384 (1991-11-01), Yokogawa
patent: 5103192 (1992-04-01), Sekine et al.
patent: 5184350 (1993-02-01), Dara
patent: 5399995 (1995-03-01), Kardontchik et al.
Chin Wellington
Luu Huong
NEC Corporation
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